Stochastic Memristive Interface for Neural Signal Processing

We propose a memristive interface consisting of two FitzHugh–Nagumo electronic neurons connected via a metal–oxide (Au/Zr/ZrO2(Y)/TiN/Ti) memristive synaptic device. We create a hardware–software complex based on a commercial data acquisition system, which records a signal generated by a presynaptic electronic neuron and transmits it to a postsynaptic neuron through the memristive device. We demonstrate, numerically and experimentally, complex dynamics, including chaos and different types of neural synchronization. The main advantages of our system over similar devices are its simplicity and real-time performance. A change in the amplitude of the presynaptic neurogenerator leads to the potentiation of the memristive device due to the self-tuning of its parameters. This provides an adaptive modulation of the postsynaptic neuron output. The developed memristive interface, due to its stochastic nature, simulates a real synaptic connection, which is very promising for neuroprosthetic applications.

A Codesigned Integrated Photonic Electronic Neuron

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage. In this paper we introduce a precision-scalable integrated photonic-electronic multiply-accumulate neuron, namely PEMAN. The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device, based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front end, has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed with resolution and power consumption, it outperforms its analog electronics counterparts both in terms of speed and power consumption, and brings substantial improvements also compared to a leading GPU.

A Codesigned Integrated Photonic Electronic Neuron

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage. In this paper we introduce a precision-scalable integrated photonic-electronic multiply-accumulate neuron, namely PEMAN. The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device, based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front end, has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed with resolution and power consumption, it outperforms its analog electronics counterparts both in terms of speed and power consumption, and brings substantial improvements also compared to a leading GPU.

Memristor Synapse-Based Morris–Lecar Model: Bifurcation Analyses and FPGA-Based Validations for Periodic and Chaotic Bursting/Spiking Firings

Electromagnetic induction current sensed by the membrane potential in biological neurons can be characterized with a memristor synapse, which can be employed to demonstrate the real oscillating voltage patterns of Barnacle muscle fibers. This paper presents a 3D autonomous memristor synapse-based Morris–Lecar (abbreviated as m-ML) model, which is implemented through introducing a memristor synapse-based induction current to substitute the externally applied current in an existing 2D nonautonomous Morris–Lecar model. Making use of one- and two-parameter bifurcation plots and time-domain representations, diverse period-adding bifurcations as well as abundant periodic and chaotic burst firings are demonstrated. Through constructing the fold and Hopf bifurcation sets of fast spiking subsystem, bifurcation analyses of these chaotic and periodic burst firings are carried out. Moreover, the periodic and chaotic spiking firings and coexisting firing behaviors are illustrated by using one- and two-parameter bifurcation plots and local attraction basins. Finally, based on a field programmable gate array (FPGA) board, a compact digital electronic neuron is fabricated for the 3D m-ML model, from which periodic and chaotic bursting/spiking firings are experimentally measured to verify the results of the numerical simulations.

Energy efficient biomorphic pulse information coding in electronic neurons for the entrance unit of the neuroprocessor

This article studies the implementation of some well-known principles of information work of biological systems in the input unit of the neuroprocessor, including spike coding of information used in models of neural networks of the latest generation.<br> The development of modern neural network IT gives rise to a number of urgent tasks at the junction of several scientific disciplines. One of them is to create a hardware platform&nbsp;— a neuroprocessor for energy-efficient operation of neural networks. Recently, the development of nanotechnology of the main units of the neuroprocessor relies on combined memristor super-large logical and storage matrices. The matrix topology is built on the principle of maximum integration of programmable links between nodes. This article describes a method for implementing biomorphic neural functionality based on programmable links of a highly integrated 3D logic matrix.<br> This paper focuses on the problem of achieving energy efficiency of the hardware used to model neural networks. The main part analyzes the known facts of the principles of information transfer and processing in biological systems from the point of view of their implementation in the input unit of the neuroprocessor. The author deals with the scheme of an electronic neuron implemented based on elements of a 3D logical matrix. A pulsed method of encoding input information is presented, which most realistically reflects the principle of operation of a sensory biological neural system. The model of an electronic neuron for selecting ranges of technological parameters in a real 3D logic matrix scheme is analyzed. The implementation of disjunctively normal forms is shown, using the logic function in the input unit of a neuroprocessor as an example. The results of modeling fragments of electric circuits with memristors of a 3D logical matrix in programming mode are presented.<br> The author concludes that biomorphic pulse coding of standard digital signals allows achieving a high degree of energy efficiency of the logic elements of the neuroprocessor by reducing the number of valve operations. Energy efficiency makes it possible to overcome the thermal limitation of the scalable technology of three-dimensional layout of elements in memristor crossbars.

Chaotic Bursting Dynamics and Coexisting Multistable Firing Patterns in 3D Autonomous Morris–Lecar Model and Microcontroller-Based Validations

A three-dimensional (3D) autonomous Morris–Lecar (simplified as M–L) neuron model with fast and slow structures was proposed to generate periodic bursting behaviors. However, chaotic bursting dynamics and coexisting multistable firing patterns have been rarely discussed in such a 3D M–L neuron model. For some specified model parameters, MATLAB numerical plots are executed by bifurcation plots, time sequences, phase plane plots, and 0–1 tests, from which diverse forms of chaotic bursting, chaotic tonic-spiking, and periodic bursting behaviors are uncovered in the 3D M–L neuron model. Furthermore, based on the theoretically constructing fold/Hopf bifurcation sets of the fast subsystem, the bifurcation mechanism for the chaotic bursting behaviors is thereby expounded qualitatively. Particularly, through numerically plotting the attraction basins related to the initial states under two sets of specific parameters, coexisting multistable firing patterns are demonstrated in the 3D M–L neuron model also. Finally, a digitally circuit-implemented electronic neuron is generated based on a low-power microcontroller and its experimentally captured results faultlessly validate the numerical plots.