One of the limiting factors for increasing the performance of CPU computation pipeline is the pipelining of control transfer instructions. This article provides a review of the problems of raising the instruction pipeline efficiency while executing the branch instructions, by the example of microarchitecture with the implementation of open RISC-V ISA. It gives a description of the various methods of resolving the control hazards. Implementations of the various static and dynamic branch prediction methods, as well as the scheme of calculating a jump address, has been provided. For the dynamic schemes this article gives an estimate of the dependency of prediction accuracy from the size of the branch history tables. Also, it contains the results of synthesis, which allow to estimate the hardware cost of the implementation of given schemes. It has been discovered that the presence of dynamic branch prediction module at the computation pipeline is helping to raise the efficiency of pipeline processing.
