A CUDA-QUDA architecture, Hyperscale-Data Quantum GPUs

QUDA is an architecture similar to CUDA for HPC applications of Quantum GPU architectures to be used in conjunction with GPU and MCU based processing. There is no QUDA pipeline similar to a stream processing architecture or an out of order instruction pipeline. True ILP is achieved with a QUDA architecture, which is better than quasi-parallelism in a CUDA or scalar/vector architecture.Keywords: QUDA architecture, HPC, Quantum Cloud, Qiskit, spin waves, spintronic, hyper-data, quantum operating system.What:Quantum Unified Compute Architecture or QUDA architectures is the use of Q and Qiskit for a reconfigurable quantum array architecture on spintronic units with a reconfigurable scheduler for a quantum operating system.

IMPLEMENTATION OF THE BRANCH PREDICTION SCHEMES FOR THE MICROPROCESSOR OF RISC-V ARCHITECTURE

One of the limiting factors for increasing the performance of CPU computation pipeline is the pipelining of control transfer instructions. This article provides a review of the problems of raising the instruction pipeline efficiency while executing the branch instructions, by the example of microarchitecture with the implementation of open RISC-V ISA. It gives a description of the various methods of resolving the control hazards. Implementations of the various static and dynamic branch prediction methods, as well as the scheme of calculating a jump address, has been provided. For the dynamic schemes this article gives an estimate of the dependency of prediction accuracy from the size of the branch history tables. Also, it contains the results of synthesis, which allow to estimate the hardware cost of the implementation of given schemes. It has been discovered that the presence of dynamic branch prediction module at the computation pipeline is helping to raise the efficiency of pipeline processing.

Evaluation of SEE on a 32-bit Microprocessor by Laser Test and Heavy Ion Test

In this paper the SEE (single event effects) of different parts of device were explored on a 32-bit microprocessor with a five-stage instruction pipeline by laser test and heavy ion test. The cross section curves for different function units were obtained and the comparison of the dates obtained from laser test and heavy ion tests was made. In addition, laser test under different scanning steps were made which indicate that when the scanning step length is in small steps which is considerably equivalent to the laser spot size, there is little change in the number of single event errors caused by each laser pulse. Wherever with the scanning step increasing, the number of single event errors caused by each laser pulse will be reduced. Experiment results suggest that there are differences between laser test and the heavy ion test but have a similar trend. The pulsed laser is an extremely powerful and low-cost technique for SEE testing and will provide invaluable information in characterizing SEE in integrate circuits.