On Binary Representation of Integers

PRIMUS ◽  
2019 ◽  
Vol 29 (5) ◽  
pp. 474-486
Author(s):  
Vardges Melkonian
1990 ◽  
Vol 55 (1) ◽  
pp. 260-276 ◽  
Author(s):  
Serge Grigorieff

This paper is a contribution to the following natural problem in complexity theory:(*) Is there a complexity theory for isomorphism types of recursive countable relational structures? I.e. given a recursive relational structure ℛ over the set N of nonnegative integers, is there a nontrivial lower bound for the time-space complexity of recursive structures isomorphic (resp. recursively isomorphic) to ℛ?For unary recursive relations R, the answer is trivially negative: either R is finite or coinfinite or 〈N, R〉 is recursively isomorphic to 〈N, {x ϵ N: x is even}〉.The general problem for relations with arity 2 (or greater) is open.Related to this problem, a classical result (going back to S. C. Kleene [4], 1955) states that every recursive ordinal is in fact primitive recursive.In [3] Patrick Dehornoy, using methods relevant to computer science, improves this result, showing that every recursive ordinal can be represented by a recursive total ordering over N which has linear deterministic time complexity relative to the binary representation of integers. As he notices, his proof applies to every recursive total order type α such that the isomorphism type of α is not changed if points are replaced by arbitrary finite nonempty subsets of consecutive points.In this paper we extend Dehornoy's result to all recursive total orderings over N and get minimal complexity for both time and space simultaneously.


1981 ◽  
Vol 10 (130) ◽  
Author(s):  
David W. Matula ◽  
Peter Kornerup

We develop the concept of minimum weight binary continued fraction representation of a rational number as an extension of minimum weight binary radix representation of an integer. The relation of these representations to the attainment of optimum efficiency in the shift and add or subtract model of binary computer arithmetic is discussed.


2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Shahram Jahani ◽  
Azman Samsudin ◽  
Kumbakonam Govindarajan Subramanian

Public-key cryptosystems are broadly employed to provide security for digital information. Improving the efficiency of public-key cryptosystem through speeding up calculation and using fewer resources are among the main goals of cryptography research. In this paper, we introduce new symbols extracted from binary representation of integers called Big-ones. We present a modified version of the classical multiplication and squaring algorithms based on the Big-ones to improve the efficiency of big integer multiplication and squaring in number theory based cryptosystems. Compared to the adopted classical and Karatsuba multiplication algorithms for squaring, the proposed squaring algorithm is 2 to 3.7 and 7.9 to 2.5 times faster for squaring 32-bit and 8-Kbit numbers, respectively. The proposed multiplication algorithm is also 2.3 to 3.9 and 7 to 2.4 times faster for multiplying 32-bit and 8-Kbit numbers, respectively. The number theory based cryptosystems, which are operating in the range of 1-Kbit to 4-Kbit integers, are directly benefited from the proposed method since multiplication and squaring are the main operations in most of these systems.


2018 ◽  
Vol 26 (3) ◽  
pp. 223-229
Author(s):  
Hiroyuki Okazaki

Summary Binary representation of integers [5], [3] and arithmetic operations on them have already been introduced in Mizar Mathematical Library [8, 7, 6, 4]. However, these articles formalize the notion of integers as mapped into a certain length tuple of boolean values. In this article we formalize, by means of Mizar system [2], [1], the binary representation of natural numbers which maps ℕ into bitstreams.


2018 ◽  
Vol 26 (2) ◽  
pp. 91-100
Author(s):  
Rafał Ziobro

Summary Even and odd numbers appear early in history of mathematics [9], as they serve to describe the property of objects easily noticeable by human eye [7]. Although the use of parity allowed to discover irrational numbers [6], there is a common opinion that this property is “not rich enough to become the main content focus of any particular research” [9]. On the other hand, due to the use of decimal system, divisibility by 2 is often regarded as the property of the last digit of a number (similarly to divisibility by 5, but not to divisibility by any other primes), which probably restricts its use for any advanced purposes. The article aims to extend the definition of parity towards its notion in binary representation of integers, thus making an alternative to the articles grouped in [5], [4], and [3] branches, formalized in Mizar [1], [2].


PLoS ONE ◽  
2017 ◽  
Vol 12 (5) ◽  
pp. e0178090 ◽  
Author(s):  
Mingzhe Su ◽  
Yan Ma ◽  
Xiangfen Zhang ◽  
Yan Wang ◽  
Yuping Zhang

2017 ◽  
Vol 26 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Ranjan Kumar Barik ◽  
Manoranjan Pradhan ◽  
Rutuparna Panda

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.


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