scholarly journals Analysis and performance evaluation of an all-fiber wide range interrogation system for a Bragg grating sensor array

2009 ◽  
Vol 11 (5) ◽  
pp. 054004 ◽  
Author(s):  
Ginu Rajan ◽  
Yuliya Semenova ◽  
Gerald Farrell

1994 ◽  
Vol 12 (4) ◽  
pp. 700-703 ◽  
Author(s):  
G.A. Ball ◽  
W.W. Morey ◽  
P.K. Cheo


2010 ◽  
Vol 20 (02) ◽  
pp. 103-121 ◽  
Author(s):  
MOSTAFA I. SOLIMAN ◽  
ABDULMAJID F. Al-JUNAID

Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into hardware and software components for final implementation. This paper explains in detail the implementation and performance evaluation of a matrix processor called Mat-Core with SystemC (system level modeling language). Mat-Core is a research processor aiming at exploiting the increasingly number of transistors per IC to improve the performance of a wide range of applications. It extends a general-purpose scalar processor with a matrix unit. To hide memory latency, the extended matrix unit is decoupled into two components: address generation and data computation, which communicate through data queues. Like vector architectures, the data computation unit is organized in parallel lanes. However, on parallel lanes, Mat-Core can execute matrix-scalar, matrix-vector, and matrix-matrix instructions in addition to vector-scalar and vector-vector instructions. For controlling the execution of vector/matrix instructions on the matrix core, this paper extends the well known scoreboard technique. Furthermore, the performance of Mat-Core is evaluated on vector and matrix kernels. Our results show that the performance of four lanes Mat-Core with matrix registers of size 4 × 4 or 16 elements each, queues size of 10, start up time of 6 clock cycles, and memory latency of 10 clock cycles is about 0.94, 1.3, 2.3, 1.6, 2.3, and 5.5 FLOPs per clock cycle; achieved on scalar-vector multiplication, SAXPY, Givens, rank-1 update, vector-matrix multiplication, and matrix-matrix multiplication, respectively.



2011 ◽  
Vol 9 (2) ◽  
pp. 34-39 ◽  
Author(s):  
Chul-Hee Ahn ◽  
Hyoung-Hoon Kim ◽  
Sang-Hu Park ◽  
Chang-Min Son ◽  
Jeung-Sang Go


1995 ◽  
Author(s):  
Timothy A. Berkoff ◽  
Michael A. Davis ◽  
David G. Bellemore ◽  
Alan D. Kersey ◽  
Glen M. Williams ◽  
...  


2021 ◽  
Vol 29 (10) ◽  
pp. 2349-2362
Author(s):  
Yue-jie SHU ◽  
◽  
Jun WU ◽  
Shi-liang ZHOU ◽  
Jun-jie WANG ◽  
...  


Author(s):  
John W. Arkwright ◽  
Anthony W. Papageorgiou ◽  
Luke A. Parkinson ◽  
Andrew R. Karas ◽  
Kristy L. Hansen


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