scholarly journals Energy efficient quaternary capacitive DAC switching scheme using sar analog to digital converter

2021 ◽  
Vol 1913 (1) ◽  
pp. 012123
Author(s):  
S Sangewar ◽  
S Gugulothu ◽  
R Khandelwal
Keyword(s):  
Energy Efficient ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Capacitive Dac

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC

2019 ◽  
Vol 28 (13) ◽  
pp. 1930010 ◽  
Author(s):  
Shubin Liu ◽  
Haolin Han ◽  
Ruixue Ding
Keyword(s):  
Successive Approximation ◽  
Energy Efficient ◽  
Sar Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Capacitor Array ◽  
Asymmetric Capacitor ◽  
Conventional Scheme

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740051 ◽  
Author(s):  
Yunfeng Hu ◽  
Chao Xiong ◽  
Bin Li
Keyword(s):  
Power Supply ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Area Reduction ◽  
Area Efficient

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

An energy-efficient reconfigurable analog-to-digital converter for orthopedic implants

2013 ◽  
Vol 78 (1) ◽  
pp. 233-243 ◽  
Author(s):  
Wenchao Qu ◽  
Syed Kamrul Islam ◽  
Ifana Mahbub ◽  
Terence C. Randall ◽  
G. To ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Orthopedic Implants ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital
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