A novel memristive true random number generator design

2019 ◽  
Vol 38 (6) ◽  
pp. 1931-1947 ◽  
Author(s):  
Zehra Gulru Cam Taskiran ◽  
Murat Taşkıran ◽  
Mehmet Kıllıoğlu ◽  
Nihan Kahraman ◽  
Herman Sedef
Keyword(s):  
Integrated Circuits ◽  
Continuous Time ◽  
Random Number ◽  
Random Number Generator ◽  
Number Generator ◽  
Chaotic Circuit ◽  
Flip Flop ◽  
Content Type ◽  
True Random Number Generator ◽  
Chua Circuit

Purpose In this work, a true random number generator is designed by sampling the double-scroll analog continuous-time chaotic circuit signals. Methodology A Chua circuit based on memristance simulator is designed to obtain a non-linear term for a chaotic dynamic system. It is implemented on the board by using commercially available integrated circuits and passive elements. A low precision ADC which is commonly found in the market is used to sample the chaotic signals. The mathematical analysis of the chaotic circuit is verified by experimental results. Originality It is aimed to be one of the pioneering studies (including low precision ADC) in the literature on the implementation of memristive chaotic random number generators. Findings Two new methods are proposed for post-processing and creating random bit array using XOR operator and J-K flip flop. The bit stream obtained by a full-hardware implementation successfully passed the NIST-800-22 test. In this respect, the availability of the memristance simulator circuit, memristive chaotic double-scroll attractor, proposed random bit algorithm and the randomness of the memristive analog continuous-time chaotic true number generator were also verified.

0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology

2020 ◽  
Vol 14 (7) ◽  
pp. 1001-1011
Author(s):  
Dhirendra Kumar ◽  
Rahul Anand ◽  
Sajai Vir Singh ◽  
Prasanna Kumar Misra ◽  
Ashok Srivastava ◽  
...  
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Number Generator ◽  
True Random Number Generator

scholarly journals A High‐Speed True Random Number Generator Based on a Cu x Te 1− x Diffusive Memristor

2021 ◽  
pp. 2100062
Author(s):  
Kyung Seok Woo ◽  
Jaehyun Kim ◽  
Janguk Han ◽  
Jin Myung Choi ◽  
Woohyun Kim ◽  
...  
Keyword(s):  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Number Generator ◽  
True Random Number Generator

scholarly journals True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Random Number ◽  
Random Number Generator ◽  
Random Number Generation ◽  
Galois Ring ◽  
Number Generator ◽  
True Random Number Generator ◽  
Number Generation ◽  
Field Programmable ◽  
Gate Array

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

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