Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sankit Kassa ◽  
Prateek Gupta ◽  
Manoj Kumar ◽  
Thompson Stephan ◽  
Ramani Kannan

Purpose In nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits. Design/methodology/approach This paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration. Findings A new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level. Originality/value This paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Bibhash Sen ◽  
Ayush Rajoria ◽  
Biplab K. Sikdar

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.


2020 ◽  
Vol 12 ◽  
Author(s):  
Arindam Sadhu ◽  
Rimpa Dey Sarkar ◽  
Kunal Das ◽  
Debashis De ◽  
Maitreyi Ray Kanjilal

Aims: Embedded system plays a vital role in today’s life. Hence our motivation is concentrated on area-delay-energy efficient embedded system design in post-CMOS technology i.e. QCA. Objectives: The research is focused on area-delay-energy efficient configurable logic block (CLB) design for field programmable gate array architecture (FPGA) with successful simulation based on a next generation technology, Quantum-dot cellular automata. Methodology: Each proposed circuits are designed in post CMOS 4 dot 2 electron technology i.e. QCA(Quantum Dot Cellular Automata) which has been adopted in circuit implementation due to Low power dissipation, high clock frequency and high package density. Functionality of every circuit is verified by QCADesigner. QCAPro tool is used for power dissipation measurement. Results: In contrast a new approach of using de-multiplexer replacing the decoder has been introduced which results in reduction of the average energy dissipation almost 57%. A NOR based D flip-flop memory architecture and multiplexer is also used in the look up table for the configurable logic block. The proposed architecture thus reduces the overall latency. Proposed CLB is consists of 6356 number of QCA cell with covering 7.44 um2 area. Write and read latency of proposed CLB is 12 and 7.25 QCA clock respectively. Conclusion: The presented paper concludes those read and write latency reduction occurs; average energy dissipation, leakage and switching energy dissipation has been reduced massively and ensues an advantage of overall reduction of the latency for the proposed CLB in the process.


2017 ◽  
Vol 74 (5) ◽  
pp. 1994-2005 ◽  
Author(s):  
Saeed Rasouli Heikalabad ◽  
Mazaher Naji Asfestani ◽  
Mehdi Hosseinzadeh

2018 ◽  
Vol 7 (4.4) ◽  
pp. 17 ◽  
Author(s):  
Sarvarbek Erniyazov ◽  
Jun Cheol Jeon

In this paper full adder was created employing five-input majority gate according to Quantum-Dot Cellular Automata (QCA) innovation. We used the QCA logic in our modified structure to reduce the delay. That report details the structure furthermore investigate associated with QCA dependent 1-bit full adder design for minimal energy purposes. This method permits decreasing energy expenditure, delay, additionally location involving electronic circuits.  


Optik ◽  
2016 ◽  
Vol 127 (20) ◽  
pp. 8576-8591 ◽  
Author(s):  
Trailokya Nath Sasamal ◽  
Ashutosh Kumar Singh ◽  
Anand Mohan

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