scholarly journals Design of Efficient Full Adder in Quantum-Dot Cellular Automata

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Bibhash Sen ◽  
Ayush Rajoria ◽  
Biplab K. Sikdar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Design ◽  
Majority Gate ◽  
Feature Size ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
High Level

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

scholarly journals Design and Implementation of Novel Efficient Full Adder/Subtractor Circuits Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (18) ◽  
pp. 8717
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Single Layer ◽  
Building Blocks ◽  
Full Adder ◽  
Cmos Technology ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
Nanoscale Level

One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite and computing circuit, performing both the addition and the subtraction processes, is of particular importance. This paper implements three new Full Adder/Subtractor circuits with the lowest number of cells, lowest area, lowest latency, and a coplanar (single-layer) circuit design, as was shown by comparing the results obtained with those of the best previous works on this topic.

scholarly journals Nanosensor Data Processor in Quantum-Dot Cellular Automata

2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Fenghui Yao ◽  
Mohamed Saleh Zein-Sabatto ◽  
Guifeng Shao ◽  
Mohammad Bodruzzaman ◽  
Mohan Malkani
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Consumption ◽  
Input Data ◽  
Cmos Technology ◽  
Sigmoid Function ◽  
Lower Power ◽  
Quantum Dot Cellular Automata ◽  
Data Processor ◽  
High Level

Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting the number of the active majority gates, and (iii) generating the approximate sigmoid function. The whole system is designed and simulated with several different input data.

Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sankit Kassa ◽  
Prateek Gupta ◽  
Manoj Kumar ◽  
Thompson Stephan ◽  
Ramani Kannan
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Circuit Design ◽  
Mathematical Proof ◽  
Average Energy ◽  
Full Adder ◽  
Majority Gate ◽  
Content Type ◽  
Quantum Dot Cellular Automata

Purpose In nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits. Design/methodology/approach This paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration. Findings A new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level. Originality/value This paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

scholarly journals Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Bibhash Sen ◽  
Siddhant Ganeriwal ◽  
Biplab K. Sikdar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Fault Tolerant ◽  
Digital Design ◽  
Quantum Cost ◽  
Quantum Dot Cellular Automata ◽  
Additional Cell ◽  
Potential Alternative ◽  
Fault Tolerant Systems ◽  
Reversible Alu

Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.

scholarly journals Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (24) ◽  
pp. 12157
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar ◽  
Khan A. Wahid
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gate ◽  
Logic Gates ◽  
Full Adder ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Xor Gate ◽  
Design Complexity ◽  
Quantum Dot Cellular Automata

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops

2015 ◽  
Vol 24 (10) ◽  
pp. 1550153 ◽  
Author(s):  
Shaahin Angizi ◽  
Samira Sayedsalehi ◽  
Arman Roohi ◽  
Nader Bagherzadeh ◽  
Keivan Navi
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
State Of The Art ◽  
Cmos Technology ◽  
Second Step ◽  
Majority Gate ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Majority Function ◽  
Functional Correctness

Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very interesting field of research in QCA domain. In this paper, we are going to propose novel nanotechnology-compatible designs based on the majority gate structures. In the first step, this objective is accomplished by QCA implementation of two well-organized JK flip-flop designs and in the second step; synchronous counters with different sizes are presented as an application. To evaluate functional correctness of the proposed designs and compare with state-of-the-art, QCADesigner tool is employed.

Implementation of Full Adder Using 5-Input Majority Gate

2018 ◽  
Vol 7 (4.4) ◽  
pp. 17 ◽  
Author(s):  
Sarvarbek Erniyazov ◽  
Jun Cheol Jeon
Keyword(s):  
Energy Expenditure ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Full Adder ◽  
Minimal Energy ◽  
Electronic Circuits ◽  
Majority Gate ◽  
Quantum Dot Cellular Automata

In this paper full adder was created employing five-input majority gate according to Quantum-Dot Cellular Automata (QCA) innovation. We used the QCA logic in our modified structure to reduce the delay. That report details the structure furthermore investigate associated with QCA dependent 1-bit full adder design for minimal energy purposes. This method permits decreasing energy expenditure, delay, additionally location involving electronic circuits.  

Design of a New Multiplexer Structure Based on a New Fault-Tolerant Majority Gate in Quantum-Dot Cellular Automata

2021 ◽  
Author(s):  
Yaser Rahmani ◽  
Saeed Rasouli Heikalabad ◽  
Mohammad Mosleh
Keyword(s):  
Fault Tolerance ◽  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Fault Tolerant ◽  
Cmos Technology ◽  
Good Alternative ◽  
Majority Gate ◽  
Power Efficient ◽  
Quantum Dot Cellular Automata

Abstract Quantum-dot Cellular Automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells, and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement.

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