Study of temperature reliability for a parallel high-efficiency class-E power amplifier

Circuit World ◽  
2017 ◽  
Vol 43 (3) ◽  
pp. 111-117 ◽  
Author(s):  
Qian Lin ◽  
Haifeng Wu ◽  
Xi Li

Purpose The purpose of this paper is to investigate the temperature reliability for a parallel high-efficiency class-E power amplifier (PA). Design/methodology/approach To explore the relationship between temperature and direct current (DC) characteristics, output power, S parameters and efficiency of the PA quantitatively, a series of reliability experiments have been designed and conducted to study the temperature reliability for this PA. Findings From the results, the prominent performance degradation even failure is found during the testing. Furthermore, the thermal shock test can cause permanent failure, which is a great threat for PA. Research limitations/implications Therefore, to ensure the good performance, the influence of temperature on PA reliability should be carefully considered during the stage of PA design. Practical implications All these can provide important guidance for the reliability design of PA. Social implications All these can give some important guidance for PA application. Originality/value In addition, PA is usually designed according to the electrical properties at the room temperature. From the results above, it can be concluded that it may be unable to satisfy the performance requirement at high temperature. In turn, if it is designed according to the electrical properties at low temperature, the transistor often works in the super-saturated state, the reliability of PA will become the new problem. Therefore, to ensure the good performance, the influence of temperature on PA reliability should be carefully considered during the design.

2015 ◽  
Vol E98.C (4) ◽  
pp. 377-379
Author(s):  
Jonggyun LIM ◽  
Wonshil KANG ◽  
Kang-Yoon LEE ◽  
Hyunchul KU

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 243-248
Author(s):  
Min Liu ◽  
Panpan Xu ◽  
Jincan Zhang ◽  
Bo Liu ◽  
Liwen Zhang

Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.


2020 ◽  
Vol 68 (9) ◽  
pp. 3732-3744
Author(s):  
Zhenxing Yang ◽  
Mingyu Li ◽  
Zhijiang Dai ◽  
Changzhi Xu ◽  
Yi Jin ◽  
...  

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