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A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
◽
10.1109/apccas.2008.4746115
◽
2008
◽
Cited By ~ 2
Author(s):
Chi-Shuang Oulee
◽
Rong-Jyi Yang
Keyword(s):
Clock And Data Recovery
◽
Data Recovery
◽
Digital Clock
Download Full-text
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References
A 10Gbps half-rate digital clock and data recovery circuit for 60GHz receiver in 65nm CMOS
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
◽
10.1109/icsict.2016.7998977
◽
2016
◽
Author(s):
Zhi-Ran Liu
◽
Zheng-Song
◽
Ying-Hang Wu
◽
Yu-Tian Li
◽
Bao-Yong Chi
Keyword(s):
Clock And Data Recovery
◽
Data Recovery
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Digital Clock
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All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology
AEU - International Journal of Electronics and Communications
◽
10.1016/j.aeue.2019.02.020
◽
2019
◽
Vol 103
◽
pp. 1-12
◽
Cited By ~ 4
Author(s):
Sanaz Salem
◽
Mohsen Saneei
Keyword(s):
Clock And Data Recovery
◽
Cmos Technology
◽
Data Recovery
◽
Digital Clock
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A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2015.2409987
◽
2016
◽
Vol 24
(2)
◽
pp. 578-586
◽
Cited By ~ 8
Author(s):
Shuai Chen
◽
Hao Li
◽
Patrick Yin Chiang
Keyword(s):
Clock And Data Recovery
◽
High Density
◽
Data Recovery
◽
Digital Clock
◽
28 Nm
◽
Area Efficient
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A fast-locking all-digital clock and data recovery circuit using successive approximation
2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)
◽
10.1109/mwscas.2016.7869960
◽
2016
◽
Cited By ~ 1
Author(s):
Ahmed E. AbdelRahman
◽
Sameh A. Ibrahim
Keyword(s):
Successive Approximation
◽
Clock And Data Recovery
◽
Data Recovery
◽
Digital Clock
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Hardware‐efficient phase‐detection technique for digital clock and data recovery
Electronics Letters
◽
10.1049/el.2012.3722
◽
2013
◽
Vol 49
(1)
◽
pp. 20-22
Author(s):
A. Zargaran‐Yazd
◽
K. Keikhosravy
◽
H. Rashtian
◽
S. Mirabbasi
Keyword(s):
Clock And Data Recovery
◽
Data Recovery
◽
Detection Technique
◽
Phase Detection
◽
Digital Clock
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A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2015.2418277
◽
2016
◽
pp. 1-1
◽
Cited By ~ 2
Author(s):
Guoying Wu
◽
Deping Huang
◽
Jingxiao Li
◽
Ping Gui
◽
Tianwei Liu
◽
...
Keyword(s):
Clock And Data Recovery
◽
Data Recovery
◽
Digital Clock
◽
High Linearity
◽
Phase Interpolator
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Behavioral test benches for digital clock and data recovery circuits using verilog-A
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.
◽
10.1109/cicc.2005.1568664
◽
2006
◽
Cited By ~ 5
Author(s):
S.I. Ahmed
◽
K. Orthner
◽
T.A. Kwasniewski
Keyword(s):
Clock And Data Recovery
◽
Data Recovery
◽
Behavioral Test
◽
Digital Clock
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Simulation of Digital Clock and Data Recovery of Strongly Disturbed Signals
2007 17th International Conference Radioelektronika
◽
10.1109/radioelek.2007.371478
◽
2007
◽
Cited By ~ 1
Author(s):
Michal Kubicek
Keyword(s):
Clock And Data Recovery
◽
Data Recovery
◽
Digital Clock
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Design and Characterization of Low Power and Low Noise Truly All-Digital Clock and Data Recovery Circuit for SERDES Devices
Journal of Low Power Electronics
◽
10.1166/jolpe.2013.1241
◽
2013
◽
Vol 9
(1)
◽
pp. 63-72
◽
Cited By ~ 1
Author(s):
Maher Assaad
◽
Mohammed H. Alser
◽
Amine Bermak
Keyword(s):
Low Power
◽
Clock And Data Recovery
◽
Low Noise
◽
Data Recovery
◽
Digital Clock
Download Full-text
Loop latency reduction technique for all-digital clock and data recovery circuits
2009 IEEE Asian Solid-State Circuits Conference
◽
10.1109/asscc.2009.5357247
◽
2009
◽
Cited By ~ 5
Author(s):
I-Fong Chen
◽
Rong-Jyi Yang
◽
Shen-Iuan Liu
Keyword(s):
Clock And Data Recovery
◽
Reduction Technique
◽
Data Recovery
◽
Latency Reduction
◽
Digital Clock
Download Full-text
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