Design and Characterization of Low Power and Low Noise Truly All-Digital Clock and Data Recovery Circuit for SERDES Devices

Journal of Low Power Electronics ◽

10.1166/jolpe.2013.1241 ◽

2013 ◽

Vol 9 (1) ◽

pp. 63-72 ◽

Author(s):

Maher Assaad ◽

Mohammed H. Alser ◽

Amine Bermak

Keyword(s):

Low Power ◽

Clock And Data Recovery ◽

Low Noise ◽

Data Recovery ◽

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A 10Gbps half-rate digital clock and data recovery circuit for 60GHz receiver in 65nm CMOS

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2016.7998977 ◽

2016 ◽

Author(s):

Zhi-Ran Liu ◽

Zheng-Song ◽

Ying-Hang Wu ◽

Yu-Tian Li ◽

Bao-Yong Chi

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

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Design of a low power Delay Locked Loop based Clock and Data Recovery circuit

2011 Annual IEEE India Conference ◽

10.1109/indcon.2011.6139507 ◽

2011 ◽

Author(s):

Vivek Kumar ◽

Mamta Khosla

Keyword(s):

Low Power ◽

Clock And Data Recovery ◽

Data Recovery ◽

Delay Locked Loop

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A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) ◽

10.1109/icecs.2018.8617976 ◽

2018 ◽

Author(s):

Ryosuke Noguchi ◽

Atsuto Imajo ◽

Toshiyuki Inoue ◽

Akira Tsuchiya ◽

Keiji Kishine

Keyword(s):

Low Power ◽

Clock And Data Recovery ◽

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All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology

AEU - International Journal of Electronics and Communications ◽

10.1016/j.aeue.2019.02.020 ◽

2019 ◽

Vol 103 ◽

pp. 1-12 ◽

Author(s):

Sanaz Salem ◽

Mohsen Saneei

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

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A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2015.2409987 ◽

2016 ◽

Vol 24 (2) ◽

pp. 578-586 ◽

Author(s):

Shuai Chen ◽

Hao Li ◽

Patrick Yin Chiang

Keyword(s):

Clock And Data Recovery ◽

High Density ◽

Data Recovery ◽

Digital Clock ◽

28 Nm ◽

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A wide range, low power clock and data recovery scheme for RFID tags

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-011-9744-0 ◽

2011 ◽

Vol 71 (1) ◽

pp. 101-106 ◽

Author(s):

Hang Yu ◽

Yan Li ◽

Lai Jiang ◽

Zhen Ji

Keyword(s):

Low Power ◽

Clock And Data Recovery ◽

Data Recovery ◽

Rfid Tags ◽

Recovery Scheme

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A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2008.4746115 ◽

2008 ◽

Author(s):

Chi-Shuang Oulee ◽

Rong-Jyi Yang

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

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A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-012-9976-7 ◽

2012 ◽

Vol 74 (2) ◽

pp. 355-364 ◽

Author(s):

Hyung-Gu Park ◽

SoYoung Kim ◽

Kang-Yoon Lee

Keyword(s):

Low Power ◽

Clock And Data Recovery ◽

Data Recovery ◽

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A fast-locking all-digital clock and data recovery circuit using successive approximation

2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2016.7869960 ◽

2016 ◽

Author(s):

Ahmed E. AbdelRahman ◽

Sameh A. Ibrahim

Keyword(s):

Successive Approximation ◽

Clock And Data Recovery ◽

Data Recovery ◽

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Hardware‐efficient phase‐detection technique for digital clock and data recovery

Electronics Letters ◽

10.1049/el.2012.3722 ◽

2013 ◽

Vol 49 (1) ◽

pp. 20-22

Author(s):

A. Zargaran‐Yazd ◽

K. Keikhosravy ◽

H. Rashtian ◽

S. Mirabbasi

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Detection Technique ◽

Phase Detection ◽

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