Microcontrollers represent unavoidable parts of state-of-the-art system-on-chips (SoCs) and they are widely embedded as IP blocks. This paper describes design steps and the application of available low-power techniques, to the design of a microcontroller IP core with 8051 instruction set, based on a prescribed standard cell libraries. Choice of the technology node and the cell library supplier is a design challenge that was considered and conclusions reached. The necessary steps of microcontroller design flow are presented which enable power reduction at several abstraction levels. An optimal microcontroller was designed to be embedded in various SoCs. The goal was to get energy-efficient microcontroller operation in applications which don't require intensive data processing. The impact of technology scaling on microcontroller energy efficiency is considered by comparison of the results obtained from implementations in three standard cell technologies. Moreover, power dissipation models are created which allow for microcontroller's power estimation in low throughput sensors networks applications.
Testability-Aware Low Power Controller Design with Evolutionary Learning