On-chip ΔI noise in the power distribution networks of high speed CMOS integrated circuits

2002 ◽  
Author(s):  
K.T. Tang ◽  
E.G. Friedman
Keyword(s):  
Integrated Circuits ◽  
Power Distribution ◽  
High Speed ◽  
Distribution Networks ◽  
Cmos Integrated Circuits ◽  
Power Distribution Networks ◽  
On Chip

scholarly journals On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

2011 ◽  
Vol 23 (2) ◽  
pp. 245-265 ◽  
Author(s):  
MARIA AGUARELES ◽  
JAUME HARO ◽  
JOSEP RIUS ◽  
J. SOLÀ-MORALES
Keyword(s):  
Integrated Circuits ◽  
Asymptotic Formula ◽  
Power Distribution ◽  
Voltage Drop ◽  
Special Functions ◽  
Distribution Networks ◽  
Power Distribution Networks ◽  
Power Distribution Network ◽  
On Chip ◽  
Solutions Of Equations

We present a new asymptotic formula for the maximum static voltage in a simplified model for on-chip power distribution networks of array bonded integrated circuits. In this model the voltage is the solution of the Poisson's equation in an infinite planar domain whose boundary is an array of circular pads of radius ϵ, and we deal with the singular limit ϵ → 0 case. In comparison with approximations that appear in the electronics engineering literature, our formula is more complete, since we have obtained terms up to order ϵ15. A procedure will be presented to compute all the successive terms, which can be interpreted by using multipole solutions of equations involving spatial derivatives of δ-functions. To deduce the formula, we use the method of matched asymptotic expansions. Our results are completely analytical and we make an extensive use of special functions and the Gauss constant G.

Power Distribution Networks with On-Chip Decoupling Capacitors

2011 ◽  
Author(s):  
Renatas Jakushokas ◽  
Mikhail Popovich ◽  
Andrey V. Mezhiba ◽  
Selçuk Köse ◽  
Eby G. Friedman
Keyword(s):  
Power Distribution ◽  
Distribution Networks ◽  
Power Distribution Networks ◽  
Decoupling Capacitors ◽  
On Chip

scholarly journals The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

2014 ◽  
Vol 25 (5) ◽  
pp. 531-551
Author(s):  
TOM CARROLL ◽  
JOAQUIM ORTEGA-CERDÀ
Keyword(s):  
Power Distribution ◽  
Complex Analysis ◽  
Voltage Drop ◽  
Elliptic Functions ◽  
Distribution Networks ◽  
Power Distribution Networks ◽  
Power Distribution Network ◽  
On Chip ◽  
Geometric Arrangements ◽  
Maximum Voltage

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.

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