A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

A bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

Nyquist Model based Thermal Noise AnalysisFrom Passive Components to CMOS Circuits

The analysis of thermal noise in network components that have resistive properties is presented. Noise analysis, based on the Nyquist model, is calculated as the rms (voltage or current equivalent) noise generated by a transimpedance, which is the concept used by general-purpose circuit simulators like Spice. It shows how this concept is used and understood in RC circuits, and how to evaluate its effect in analog circuits, particularly in the design of CMOS integrated circuits. It is shown that the magnitude of the noise generated by a transistor is not of interest, but the net effect of all sources of thermal noise in circuits and systems, fundamentally, when the miniaturization of the transistor implies reducing the value of the supply voltages. The ultimate purpose of this contribution is to highlight the importance of noise analysis using fundamentals of circuit theory and identify the variables under the designer's control to minimize their effect on the performance of the circuits under development.

FEATURES OF THE TECHNOLOGICAL PROCESS OF MANUFACTURING SPACE-BASED MICROCHIPS USING CMOS KNS TECHNOLOGY

The article deals with the technological process of manufacturing CMOS integrated circuits on KNS (silicon on sapphire) structures for space purposes. The technology is based on an n-type CMOS process with one level of polysilicon and two levels of metal. The components of the technological process are analyzed. The sequence of the technological process and its features are given. An example of a description of one of the elements is considered.