Power Distribution Networks in High Speed Integrated Circuits; Andrey Mezhiba, Eby Friedman. Kluwer Academic Publishers, Boston; 2004. Hardcover, 280pp, plus XXIII, 129 euro. ISBN 1-4020-7534-0

2004 ◽  
Vol 44 (8) ◽  
pp. 1277-1278
Author(s):  
Mile Stojcev
Keyword(s):  
Integrated Circuits ◽  
Power Distribution ◽  
High Speed ◽  
Distribution Networks ◽  
Power Distribution Networks

scholarly journals On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

2011 ◽  
Vol 23 (2) ◽  
pp. 245-265 ◽  
Author(s):  
MARIA AGUARELES ◽  
JAUME HARO ◽  
JOSEP RIUS ◽  
J. SOLÀ-MORALES
Keyword(s):  
Integrated Circuits ◽  
Asymptotic Formula ◽  
Power Distribution ◽  
Voltage Drop ◽  
Special Functions ◽  
Distribution Networks ◽  
Power Distribution Networks ◽  
Power Distribution Network ◽  
On Chip ◽  
Solutions Of Equations

We present a new asymptotic formula for the maximum static voltage in a simplified model for on-chip power distribution networks of array bonded integrated circuits. In this model the voltage is the solution of the Poisson's equation in an infinite planar domain whose boundary is an array of circular pads of radius ϵ, and we deal with the singular limit ϵ → 0 case. In comparison with approximations that appear in the electronics engineering literature, our formula is more complete, since we have obtained terms up to order ϵ15. A procedure will be presented to compute all the successive terms, which can be interpreted by using multipole solutions of equations involving spatial derivatives of δ-functions. To deduce the formula, we use the method of matched asymptotic expansions. Our results are completely analytical and we make an extensive use of special functions and the Gauss constant G.

scholarly journals Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters

2018 ◽  
Vol 10 (1) ◽  
pp. 27
Author(s):  
A. S. R. Murthy ◽  
Sridhar T.
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Power Distribution ◽  
High Speed ◽  
Low Voltage ◽  
Data Communication ◽  
Distribution Networks ◽  
Propagation Delay ◽  
Switched Capacitor ◽  
Power Efficient

<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

scholarly journals Comparison of Economical and Technical Photovoltaic Hosting Capacity Limits in Distribution Networks

Energies ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2405
Author(s):  
Samar Fatima ◽  
Verner Püvi ◽  
Ammar Arshad ◽  
Mahdi Pourakbari-Kasmaei ◽  
Matti Lehtonen
Keyword(s):  
Power Distribution ◽  
Renewable Energy Sources ◽  
Distribution Networks ◽  
Power Distribution Networks ◽  
Network Losses ◽  
Network Costs ◽  
Cost And Benefit Analysis ◽  
Cost Parameters ◽  
The Cost ◽  
Pv Penetration

Power distribution networks are transitioning from passive towards active networks considering the incorporation of distributed generation. Traditional energy networks require possible system upgrades due to the exponential growth of non-conventional energy resources. Thus, the cost concerns of the electric utilities regarding financial models of renewable energy sources (RES) call for the cost and benefit analysis of the networks prone to unprecedented RES integration. This paper provides an evaluation of photovoltaic (PV) hosting capacity (HC) subject to economical constraint by a probabilistic analysis based on Monte Carlo (MC) simulations to consider the stochastic nature of loads. The losses carry significance in terms of cost parameters, and this article focuses on HC investigation in terms of losses and their associated cost. The network losses followed a U-shaped trajectory with increasing PV penetration in the distribution network. In the investigated case networks, increased PV penetration reduced network costs up to around 40%, defined as a ratio to the feeding secondary transformer rating. Above 40%, the losses started to increase again and at 76–87% level, the network costs were the same as in the base cases of no PVs. This point was defined as the economical PV HC of the network. In the case of networks, this level of PV penetration did not yet lead to violations of network technical limits.

Sign in / Sign up

Export Citation Format

Share Document