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High Level Test Generation / SW based Embedded Test
14th Asian Test Symposium (ATS'05)
◽
10.1109/ats.2005.64
◽
2005
◽
Author(s):
P. Parvathala
Keyword(s):
Test Generation
◽
Embedded Test
◽
High Level
Download Full-text
Related Documents
Cited By
References
High Level Test Generation via Process Composition
Designing Correct Circuits - Workshops in Computing
◽
10.1007/978-1-4471-3544-9_6
◽
1991
◽
pp. 99-119
Author(s):
Venkatesh Akella
◽
Ganesh Gopalakrishnan
Keyword(s):
Test Generation
◽
High Level
◽
Process Composition
Download Full-text
Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design
◽
10.1109/isvd.1991.185103
◽
1991
◽
Author(s):
S. Kode
Keyword(s):
Test Generation
◽
System Level
◽
Circuit Partitioning
◽
Speed Up
◽
High Level
Download Full-text
Synthesis of high-level requirements models for automatic test generation
Proceedings. Eighth Annual IEEE International Conference and Workshop On the Engineering of Computer Based Systems-ECBS 2001
◽
10.1109/ecbs.2001.922408
◽
2002
◽
Cited By ~ 3
Author(s):
P. Gupta
◽
S.I. Cunning
◽
J.W. Rozenblit
Keyword(s):
Test Generation
◽
Automatic Test Generation
◽
Automatic Test
◽
High Level
◽
Requirements Models
Download Full-text
High-level test generation for VLSI
Computer
◽
10.1109/2.25379
◽
1989
◽
Vol 22
(4)
◽
pp. 16-24
◽
Cited By ~ 6
Author(s):
D. Bhattacharya
◽
B.T. Murray
◽
J.P. Hayes
Keyword(s):
Test Generation
◽
High Level
Download Full-text
Test Generation and Evaluation from High-Level Properties for Common Criteria Evaluations -- The TASCCC Testing Tool
2013 IEEE Sixth International Conference on Software Testing, Verification and Validation
◽
10.1109/icst.2013.60
◽
2013
◽
Cited By ~ 2
Author(s):
Frederic Dadeau
◽
Kalou Cabrera Castillos
◽
Yves Ledru
◽
Taha Triki
◽
German Vega
◽
...
Keyword(s):
Test Generation
◽
Common Criteria
◽
Testing Tool
◽
High Level
Download Full-text
High-level path activation technique to speed up sequential circuit test generation
European Test Workshop 1999 (Cat. No.PR00390)
◽
10.1109/etw.1999.804289
◽
2003
◽
Cited By ~ 2
Author(s):
J. Raik
◽
R. Ubar
Keyword(s):
Test Generation
◽
Activation Technique
◽
Sequential Circuit
◽
Speed Up
◽
High Level
Download Full-text
Test Generation for Very High-Level Design Language (VHDL) Specifications Used in Avionics
10.21236/ada416255
◽
2002
◽
Author(s):
Mohamed F. Chouikha
Keyword(s):
Test Generation
◽
Design Language
◽
Level Design
◽
High Level
◽
Very High
Download Full-text
Designing for high-level test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/43.55212
◽
1990
◽
Vol 9
(7)
◽
pp. 752-766
◽
Cited By ~ 4
Author(s):
D. Bhattacharya
◽
J.P. Hayes
Keyword(s):
Test Generation
◽
High Level
Download Full-text
High-level test generation using symbolic scheduling
Proceedings of 1995 IEEE International Test Conference (ITC)
◽
10.1109/test.1995.529887
◽
2002
◽
Cited By ~ 13
Author(s):
M.C. Hansen
◽
J.P. Hayes
Keyword(s):
Test Generation
◽
High Level
Download Full-text
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2010.2043571
◽
2010
◽
Vol 29
(5)
◽
pp. 737-748
◽
Cited By ~ 3
Author(s):
Bijan Alizadeh
◽
Mohammad Mirzaei
◽
Masahiro Fujita
Keyword(s):
Test Generation
◽
Sequential Circuits
◽
Polynomial Model
◽
High Level
Download Full-text
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