High-level path activation technique to speed up sequential circuit test generation

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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High Level Test Generation / SW based Embedded Test

14th Asian Test Symposium (ATS'05) ◽

10.1109/ats.2005.64 ◽

2005 ◽

Author(s):

P. Parvathala

Keyword(s):

Test Generation ◽

Embedded Test ◽

High Level

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Illegal state space identification for sequential circuit test generation

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761213 ◽

2003 ◽

Cited By ~ 8

Author(s):

M. Konijnenburg ◽

J. van der Linden ◽

A. van de Goor

Keyword(s):

State Space ◽

Test Generation ◽

Sequential Circuit

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An Open-Source Cloud-FPGA Gene Regulatory Accelerator

10.5753/wscad.2021.18527 ◽

2021 ◽

Author(s):

Lucas Bragança ◽

Jeronimo Penha ◽

Michael Canesche ◽

Dener Ribeiro ◽

José Augusto M. Nacif ◽

...

Keyword(s):

Open Source ◽

Gene Regulatory Networks ◽

High Performance ◽

Regulatory Networks ◽

Cloud Services ◽

On Demand ◽

Speed Up ◽

Gene Regulatory ◽

High Level ◽

Better Than

FPGAs are suitable to speed up gene regulatory network (GRN) algorithms with high throughput and energy efficiency. In addition, virtualizing FPGA using hardware generators and cloud resources increases the computing ability to achieve on-demand accelerations across multiple users. Recently, Amazon AWS provides high-performance Cloud's FPGAs. This work proposes an open source accelerator generator for Boolean gene regulatory networks. The generator automatically creates all hardware and software pieces from a high-level GRN description. We evaluate the accelerator performance and cost for CPU, GPU, and Cloud FPGA implementations by considering six GRN models proposed in the literature. As a result, the FPGA accelerator is at least 12x faster than the best GPU accelerator. Furthermore, the FPGA reaches the best performance per dollar in cloud services, at least 5x better than the best GPU accelerator.

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PENENTUAN LOKASI TOWER CRANE PADA PROYEK KONSTRUKSI BERBASIS SIMULASI

JMTS: Jurnal Mitra Teknik Sipil ◽

10.24912/jmts.v3i4.8694 ◽

2020 ◽

Vol 3 (4) ◽

pp. 1305

Author(s):

Gerwyn Persulessy ◽

Basuki Anondho

Keyword(s):

Travel Time ◽

Construction Projects ◽

Tower Crane ◽

Location Determination ◽

Heavy Equipment ◽

Total Travel Time ◽

Speed Up ◽

High Level ◽

Map Data ◽

Geometric Layout

Development of high-level building construction projects that require complex equipment that can be used in high-level construction, equipment used to help complete construction projects called heavy equipment. One of the heavy equipment used in high-rise buildings is a tower crane. The use and layout of tower cranes can speed up the schedule and save on project costs. Therefore many methods have been developed to determine the tower crane layout. This study will discuss determining the location of tower cranes by discussing simulations. The location will be determined based on the site map data which is processed in the form of a geometric arrangement and tower crane data specifications. Location determination is done by comparing the total travel time of several simulated locations according to several different speed criteria in a construction project. Speed criteria are divided into four times the jib speed and trolley speed. Location of the location with the total travel time will be taken as the final result. Different speed criteria will make the total travel time change. ABSTRAKPerkembangan proyek pembangunan gedung bertingkat tinggi yang semakin kompleks menyebabkan diperlukannya peralatan yang dapat mempermudah pembangunan gedung bertingkat, peralatan yang digunakan untuk membantu menyelesaikan tugas konstruksi disebut alat berat. Salah satu peralatan berat yang digunakan pada gedung bertingkat tinggi adalah tower crane. Penggunaan dan tata letak tower crane yang baik dapat mempercepat jadwal dan menghemat biaya proyek. Oleh karena itu banyak dikembangkan metode-metode untuk menentukan tata letak tower crane. Penelitian ini akan membahas penetapan letak lokasi tower crane dengan pendekatan simulasi. Letak lokasi akan ditetapkan berdasarkan data site map yang diolah dalam bentuk geometric layout dan data spesifikasi tower crane. Penetapan lokasi dilakukan dengan cara membandingkan total travel time dari beberapa lokasi yang disimulasi sesuai dengan beberapa kriteria kecepatan yang berbeda-beda pada suatu proyek konstruksi. Kriteria kecepatan terbagi menjadi empat berdasarkan besarnya kecepatan jib dan kecepatan trolley. Letak lokasi dengan total travel time terkecil akan diambil sebagai hasil akhir. Kriteria-kriteria kecepatan yang berbeda disimulasi akan membuat total travel time berubah.

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Deep Learning Strategies for ProtoDUNE Raw Data Denoising

Computing and Software for Big Science ◽

10.1007/s41781-021-00077-9 ◽

2022 ◽

Vol 6 (1) ◽

Author(s):

Marco Rossi ◽

Sofia Vallecorsa

Keyword(s):

Neural Networks ◽

Deep Learning ◽

Learning Strategies ◽

Simulation Data ◽

Raw Data ◽

Digital Detector ◽

Speed Up ◽

Neural Network Hardware ◽

Graph Neural Networks ◽

High Level

AbstractIn this work, we investigate different machine learning-based strategies for denoising raw simulation data from the ProtoDUNE experiment. The ProtoDUNE detector is hosted by CERN and it aims to test and calibrate the technologies for DUNE, a forthcoming experiment in neutrino physics. The reconstruction workchain consists of converting digital detector signals into physical high-level quantities. We address the first step in reconstruction, namely raw data denoising, leveraging deep learning algorithms. We design two architectures based on graph neural networks, aiming to enhance the receptive field of basic convolutional neural networks. We benchmark this approach against traditional algorithms implemented by the DUNE collaboration. We test the capabilities of graph neural network hardware accelerator setups to speed up training and inference processes.

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An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C

VLSI Design ◽

10.1155/2012/793196 ◽

2012 ◽

Vol 2012 ◽

pp. 1-11

Author(s):

M. Walton ◽

O. Ahmed ◽

G. Grewal ◽

S. Areibi

Keyword(s):

Optimization Problems ◽

Scatter Search ◽

Population Based ◽

Field Programmable ◽

Speed Up ◽

Time Required ◽

High Level ◽

Level Parallelism ◽

Code Optimizations ◽

Established Population

Scatter Search is an effective and established population-based metaheuristic that has been used to solve a variety of hard optimization problems. However, the time required to find high-quality solutions can become prohibitive as problem sizes grow. In this paper, we present a hardware implementation of Scatter Search on a field-programmable gate array (FPGA). Our objective is to improve the run time of Scatter Search by exploiting the potentially massive performance benefits that are available through the native parallelism in hardware. When implementing Scatter Search we employ two different high-level languages (HLLs): Handel-C and Impulse-C. Our empirical results show that by effectively exploiting source-code optimizations, data parallelism, and pipelining, a 28x speed up over software can be achieved.

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