Analysis of On-Silicon-Vias for an Advanced RF-CMOS Process: Experimental Characterization and Modeling

This chapter presents a wireless interface for intra-vehicle communications (data acquisition from sensors, control, and multimedia) at 5.7 GHz. As part of the wireless interface, a RF transceiver was fabricated in the UMC 0.18 µm RF CMOS process and when activated, it presents a total power consumption of 23 mW with the voltage-supply of 1.5 V. This allows the use of only a coin-sized battery for supplying the interface. The carrier frequency can be digitally selectable and take one of 16 possible frequencies in the range 5.42-5.83 GHz, adjusted in steps of 27.12 MHz. These multiple carriers allow a better spectrum allocation and at the same time will improve the channel capacity due to the possibility to allow multiple accesses with multiple frequencies.

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A design of sub-band generator for MB-OFDM UWB application in 0.13 μm RF CMOS process

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2008.4746369 ◽

2008 ◽

Author(s):

Joon Sung Park ◽

YoungGun Pu ◽

Young-Shin Kim ◽

Chul Nam ◽

Kang-Yoon Lee

Keyword(s):

Cmos Process ◽

Rf Cmos

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An Integrated Optical Receiver in MS/RF CMOS Process

3rd IEEE International Conference on Group IV Photonics, 2006. ◽

10.1109/group4.2006.1708174 ◽

2006 ◽

Author(s):

Haijun Liu ◽

Xingsheng Xu ◽

Luhong Mao ◽

Peng Gao ◽

Hongda Chen

Keyword(s):

Optical Receiver ◽

Cmos Process ◽

Rf Cmos ◽

Integrated Optical

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A design of the frequency synthesizer for UWB application in 0.13 μm RF CMOS process

2007 IEEE International Workshop on Radio-Frequency Integration Technology ◽

10.1109/rfit.2007.4443980 ◽

2007 ◽

Author(s):

Jin-Kyung Kim ◽

Sung-Kyu Jung ◽

Ji-Hoon Jung ◽

Kang-Yoon Lee ◽

Chul Nam ◽

...

Keyword(s):

Frequency Synthesizer ◽

Cmos Process ◽

Rf Cmos

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A High Bandwidth (DC-40 GHz) Pseudo Differential Distributed Amplifier in 0.18-μm RF CMOS

Journal of Circuits System and Computers ◽

10.1142/s0218126617501912 ◽

2017 ◽

Vol 26 (12) ◽

pp. 1750191 ◽

Cited By ~ 4

Author(s):

Majid Babaeinik ◽

Massoud Dousti ◽

Mohammad Bagher Tavakoli

Keyword(s):

Return Loss ◽

Noise Figure ◽

Cmos Process ◽

Rf Cmos ◽

Bandwidth Extension ◽

Distributed Amplifier ◽

High Bandwidth ◽

Simulation Results ◽

Minimum Noise ◽

Minimum Noise Figure

This study presents a CMOS distributed amplifier (DA) with pseudo differential amplifying that achieves DC-40[Formula: see text]GHz bandwidth (BW) in 0.18-[Formula: see text]m RF CMOS process. The DA with three-stage amplifying cells was proposed to improve the DA performance. The inter-stage was composed of pseudo differential amplifying for bandwidth extension. By incorporating the pseudo differential amplifier configuration and capacitor-less circuit in the stages, the DA provides average gain and high bandwidth. The simulation results showed that the DA has a S[Formula: see text] of 6.4[Formula: see text]dB, 3-dB BW from DC up to 40[Formula: see text]GHz. It also has a minimum noise figure (NF) of 4.27[Formula: see text]dB, one dB compression point (P[Formula: see text] of [Formula: see text]3.5[Formula: see text]dBm, a high reverse isolation S[Formula: see text] of less than [Formula: see text]15[Formula: see text]dB, an input return loss S[Formula: see text] and output return loss S[Formula: see text] of less than [Formula: see text]16 and [Formula: see text]12[Formula: see text]dB, respectively. It consumes 115[Formula: see text]mW and occupies a total active area of 0.27[Formula: see text]mm2.

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