ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW

An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, the supply voltage, and the phase noise. Based on the review, the reduction in CMOS scaling decreases the transistor size in ADPLL design which leads to a smaller area and a low power dissipation. The combination of the time-to-digital (TDC) and the digital-to-time converter (DTC) that is used as the phase-frequency detector (PFD) in ADPLL is proposed to reduce the power and phase noise performance due to their high linearity design. The delay cell oscillator is found to consume more power at higher operating frequency, but it has an advantage of having less complexity and consuming less power and area in the circuit compared to the LC tank oscillator. For future work, it is recommended that an ADPLL-based LO of RFID transceiver with lowest voltage supply implementation is chosen and the use of the TDC-less as the PFD is selected due to its small area. While for the DCO, the delay cell will be designed due to its simpler implementation and occupy small area.

Design and Implementation of a Low-Cost Universal RFID Wireless Logistics Terminal in the Process of Logistics Traceability

The logistics traceability system can cover the whole process of the product from the source of production to the consumption cycle. By distinguishing the key nodes of the product in the logistics sales process, the data information of the production and storage of the corresponding product is collected and entered at the corresponding node, so that the entire process is visible and controllable. On the basis of determining the overall system plan, this paper designs and develops the UHF RFID reader system and traceability system platform. In terms of the reader system, by analyzing its core functions and performance index requirements, the overall design scheme and frame structure of the reader system’s software and hardware are determined. The main control circuit is based on the STM32F103RET6 single-chip microcomputer; the RF transceiver circuit is based on the MagicRF M100. Simultaneously, we design a variety of communication circuits including LoRa and RJ45 to facilitate wireless communication with the traceability platform. In terms of software, through the research and analysis of the EPC Class-1 Generation-2 protocol standard, the multitag anticollision algorithm—Q algorithm—is adopted. This algorithm has the advantages of high recognition efficiency and a large number of successfully recognized tags per unit time. According to the design plan, the system is wirelessly networked in the B/S mode and the product information collected through RFID technology is transmitted to the management level to dynamically understand the information dynamics of logistics in real time. Using radio frequency, computer network, communication, and other technologies, the hardware and software systems of the system are integrated. The performance indicators of the hardware system are tested through experiments, and the design indicators are compared to prove the feasibility of the equipment application. After setting up the local area network and configuring the server configuration, the traceability system was accessed and the verification of the basic functions of the system was completed. The test results show that the low-cost universal RFID wireless logistics terminal has high accuracy and real-time performance in the process of logistics traceability.

Testing of Frequency Synthesizers for ZigBee Transceivers

ZigBee is a wireless standard defined for low data rate applications with ultra-low power requirements. Devices based on this standard are expected to be low cost with a large battery life or use energy harvesting techniques.As a part of a major project for developing a fully functional RF transceiver chip complying with the standard, frequency synthesizers have been designed based on integer-N phase lock loops which are expected to work as local oscillators for both the transmitter and the receiver. The standard required the PLLs to be programmable to 16 channels in the 2.4-2.5 GHz range. One of the PLLs used an LC VCO while the other used a ring VCO. This work was meant to test these PLLs to make sure that they met the specifications required of them as per the standard.