Design of Low Noise Amplifier for WLAN using pHEMT

The low power consumption devices are frequently focused in design and manufacturing wireless communication system. This paper gives a systematic design of a low noise amplifier for WLAN application aimed to obtain minimum noise figure. The simulation result shows that the noise figure is in the appreciable level (1.67 dB). The maximum gain is greater than 10 dB. These are the predominant requirements of an LNA. Also it posses good stability and the LNA design uses pHEMT for its appreciable noise performance.

Performance Analysis of Inductive Source Degeneration Low Noise Amplifier using Multi-finger Technique

In the current paper, common source Low Noise Amplifier using inductively degenerated technique is designed to meet Radio Frequency (RF) range 2.45 GHz-2.85 GHz. The designed LNA is implemented using single and multi-finger transistor logic. The transistor geometry greater than 300 μm has been split into multiple fingers using multi-finger technology. The schematic is captured using ADS. The performance of LNA for various technologies has been analyzed using PTM 180 nm, PTM 130 nm and PTM 90 nm models. The amplifier with single transistor achieves minimum noise figure of 0.178 dB noise figure and maximum gain of 20.045 dB using 130 nm model technology for Bluetooth applications. Similarly 0.288 dB of minimum noise figure and peak gain of 17.971 dB are obtained using multi-finger MOSFET of PTM 90 nm technologyrespectively.The reverse isolation (S12) below -50 dB is achieved.

Development of Accurate BSIM4 Noise Parameters for CMOS 0.13-µm Transistors in Below 3-GHz LNA Application

Accurate transistor thermal noise model is crucial in IC design as it allows accurate selection of transistors for specific frequency application. The accuracy of the model is represented by the similarity between the simulated and the measured noise parameters (NPs). This work was based on a problem faced by a foundry concerning the dissimilarities between the measured and simulated NPs, especially minimum noise figure (NF_min) for frequencies below 3 GHz.

A High Bandwidth (DC-40 GHz) Pseudo Differential Distributed Amplifier in 0.18-μm RF CMOS

This study presents a CMOS distributed amplifier (DA) with pseudo differential amplifying that achieves DC-40[Formula: see text]GHz bandwidth (BW) in 0.18-[Formula: see text]m RF CMOS process. The DA with three-stage amplifying cells was proposed to improve the DA performance. The inter-stage was composed of pseudo differential amplifying for bandwidth extension. By incorporating the pseudo differential amplifier configuration and capacitor-less circuit in the stages, the DA provides average gain and high bandwidth. The simulation results showed that the DA has a S[Formula: see text] of 6.4[Formula: see text]dB, 3-dB BW from DC up to 40[Formula: see text]GHz. It also has a minimum noise figure (NF) of 4.27[Formula: see text]dB, one dB compression point (P[Formula: see text] of [Formula: see text]3.5[Formula: see text]dBm, a high reverse isolation S[Formula: see text] of less than [Formula: see text]15[Formula: see text]dB, an input return loss S[Formula: see text] and output return loss S[Formula: see text] of less than [Formula: see text]16 and [Formula: see text]12[Formula: see text]dB, respectively. It consumes 115[Formula: see text]mW and occupies a total active area of 0.27[Formula: see text]mm2.

The Design of a 1~13 GHz GaAs Travelling Wave Amplifier

A 4-stage travelling wave amplifier with 10dB ± 1.2 dB gain and 12 GHz bandwidth is presented in the paper. The parameters of the small signal equivalent model about the GaAs PHEMT are extracted to evaluate the characterization of the device, which is also used to design the amplifier. The amplifier has a minimum noise figure lower than 4.8 dB in the frequency range, and the S11 and S22 are below-10 dB and-7 dB, which demonstrate a good performance. The P1dB and IIP3 are 7.3 dBm and 24 dBm, respectively, and the saturation output power is above 20 dBm at 13 GHz.