Passive Components for RF-ICs

The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.

RF-MEMS Based Oscillators

Today’s high-tech consumer market demand complex, portable personal wireless consumer devices that are low-cost and have small sizes. Creative methods of combining mature integrated circuit (IC) fabrication techniques with innovative radio-frequency micro-electro-mechanical systems (RF-MEMS) devices has given birth to wireless transceiver components, which operate at higher frequencies but are manufactured at the low-cost of standard ICs. Oscillators, RF bandpass filters, and low noise amplifiers are the most critical and important modules of any wireless transceiver. Their individual characteristics determine the overall performance of a transceiver. This chapter illustrates RF-oscillators that utilize MEMS devices such as resonators, varactors, and inductors for frequency generation. Emphasis will be given on state of the art RF-MEMS components such as film bulk acoustic wave, surface acoustic wave, flexural mode resonators, lateral and vertical varactors, and solenoid and planar inductors. The advantages and disadvantages of each device structure are described, with reference to the most recent work published in the field.

Wireless Interface at 5.7 GHz for Intra-Vehicle Communications

This chapter presents a wireless interface for intra-vehicle communications (data acquisition from sensors, control, and multimedia) at 5.7 GHz. As part of the wireless interface, a RF transceiver was fabricated in the UMC 0.18 µm RF CMOS process and when activated, it presents a total power consumption of 23 mW with the voltage-supply of 1.5 V. This allows the use of only a coin-sized battery for supplying the interface. The carrier frequency can be digitally selectable and take one of 16 possible frequencies in the range 5.42-5.83 GHz, adjusted in steps of 27.12 MHz. These multiple carriers allow a better spectrum allocation and at the same time will improve the channel capacity due to the possibility to allow multiple accesses with multiple frequencies.

Optimization of Linearity in CMOS Low Noise Amplifier

In this chapter the authors evaluate a new and promising solution to the problem of power consumption based on “optimum gate biasing.” This technique consists in tracking the MOS operating region wherein the third derivation of drain current is zero. The method leads to a significant IIP3 improvement; however, the sensitivity to process drifts requires the use of a specific bias circuit to track the optimum biasing condition.

Frequency Synchronization for OFDM/OFDMA Systems

Orthogonal frequency division multiplexing (OFDM) has been the focus of many studies in wireless communications because of its high transmission capability and its robustness to the effects of frequency-selective multipath channels. However, it is well known that OFDM systems are much more sensitive to a carrier frequency offset (CFO) than single carrier schemes with the same bit rate. Therefore, a frequency synchronization process is necessary to overcome this sensitivity to frequency offset. Synchronization is performed in two stages: acquisition and tracking. After a first estimation and correction of the CFO performed in the acquisition stage, there still remains a residual frequency offset (RFO) due to real system conditions. Therefore, the RFO tracking has to be performed for all the receiving data. Frequency synchronization is even more complicated for uplink communications in OFDMA (orthogonal frequency division multiple access) systems because the base station (BS) has to deal with signals from different users in the same bandwidth. Each user’s data is affected by a different CFO. Because of this, estimation and correction of the CFOs cannot be accomplished by the same methods as in OFDM systems.

S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless Communications

This chapter presents a systematic design of a S-? fractional-N Phase-Locked Loop based on hardware description language behavioral modeling. The proposed design consists of describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The description language models of critical PLL blocks have been described in VHDL-AMS, which is an IEEE standard, to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the overall system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models in the frequency range around 2.45 GHz for wireless applications.

Simulation Techniques for Improving Fabrication Yield of RF-CMOS ICs

One of the industry sectors with the largest revenue in the telecommunication field is the wireless communications field. Wireless operators compete for being the first to place their products in the market to obtain the highest revenues. Moreover, they try to offer products that fulfill the user demands in terms of price, battery life, and product quality. All these requirements must be also fulfilled by the designer of the MMIC (Microwave Monolithic Integrated Circuits) circuits that will be used in those wireless terminals, achieving a reliable design, with high performance, low cost, and if possible, in one or two foundry iterations so as to bring the product out to the market as soon as possible. Silicon based technologies are the lowest cost. The demand to use them is simply based on that fact, but their usage in these applications is limited by the ease of use for the designer, in particular, by the lack of adequate simulation models. These technologies don’t include some essential components for the design of RF circuits, which leads to measurement results quite different from those simulated. On the other hand, GaAs based technologies, more mature in the RF and microwave field, provide very accurate models, as well as additional tools to verify the design reliability (yield and sensitivity analysis), allowing good results often with only one foundry iteration. The deep study of the problems presented when designing Si-based RF circuits will convince the reader of the need to use special tools as electromagnetic simulation or coo simulation to prevent it. The chapter provides different simulation techniques that help the designer to obtain better designs with a lower cost, as foundry iterations are reduced.

System Design Perspective

The next generation of cellular networks has evolved from voice-based to data-centric communication. The recent focus has been mainly on high data-rate services like mobile gaming, high quality music, Internet browsing, video streaming, etcetera, which consumes lots of bandwidth. This puts a severe constraint on the available radio resource. In this chapter, the IEEE 802.16 based multihop WiMAX networks (802.16j) is introduced, and the system design is explained in detail. The chapter outlines the background and the importance of multihop wireless networks, especially in the cellular domain. Different types of multihop design for WiMAX are explained, along with a detailed analysis of the effect of the number of hops in the WiMAX networks. Further, in order to support next generation rich media services, the system design requirements, and challenges for real-time video transmission are explained.

Design and Implementation of Hardware Modules for Baseband Processing in Radio Transceivers

In this chapter, the main aspects of the design of baseband hardware modules are addressed. Special attention is given to word-length optimization, implementation, and validation tasks. As a case study, the design of an equalizer for a 4G MIMO receiver is addressed. The equalizer is part of a communication system able to handle up to 32 users and provide transmission bit-rates up to 125 Mbps. The word-length optimization process will be explained first, as well as techniques to reduce computation times. Then, the case study will be presented and analyzed, and the different tasks and tools required for its implementation will be explained. FPGAs are selected as the target implementation technology due to their interest from the DSP community.

Design Issues for Multi-Mode Multi-Standard Transceivers

Multi-mode and multi-band transceivers, i.e., transceivers with the capability to operate in different frequency bands and to support different waveforms and signaling schemes, are objects of intense study. In fact, hardware reuse among different standards would help to reduce production costs, power consumption, and to increase the integration level of a given implementation. The design of such transceivers is indeed very complex, because it not only implies the choice of the architecture more suitable for the target application, but also the choice and the design of reconfigurable building blocks to perform tuning among the different standards and signaling schemes. In addition, different standards may have considerably different requirements in terms of receiver sensitivity, linearity, input dynamic range, error vector magnitude (EVM), signal bandwidth, and data rate, which in turn make the design of a multi-mode reconfigurable transceiver a very challenging task. In this chapter, the authors present the most common techniques and architecture schemes used in modern wireless communication systems supporting standards for cellular, wireless local area networks (WLAN), and wireless personal area networks (WPAN), i.e., GSM, WCDMA, IEEE 802.11 (Wi-Fi), IEEE 802.15.1 (Bluetooth), IEEE 802.15.4 (Zigbee), and IEEE 802.15.3 (UWB). State-of-the-art techniques for multi-standard cellular, WLAN, and WPAN transceivers are thoroughly analyzed and reviewed with special emphasis on those relying on bandpass sampling and multi-rate signal processing schemes.