A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process

Author(s):  
JinKyung Kim ◽  
Sung-Kyu Jung ◽  
Ji-Hoon Jung ◽  
Sang-Kyung Sung ◽  
Kang-Yoon Lee ◽  
...  
Author(s):  
Jin-Kyung Kim ◽  
Sung-Kyu Jung ◽  
Ji-Hoon Jung ◽  
Kang-Yoon Lee ◽  
Chul Nam ◽  
...  

Author(s):  
J. P. Carmo ◽  
J. H. Correia

This chapter presents a wireless interface for intra-vehicle communications (data acquisition from sensors, control, and multimedia) at 5.7 GHz. As part of the wireless interface, a RF transceiver was fabricated in the UMC 0.18 µm RF CMOS process and when activated, it presents a total power consumption of 23 mW with the voltage-supply of 1.5 V. This allows the use of only a coin-sized battery for supplying the interface. The carrier frequency can be digitally selectable and take one of 16 possible frequencies in the range 5.42-5.83 GHz, adjusted in steps of 27.12 MHz. These multiple carriers allow a better spectrum allocation and at the same time will improve the channel capacity due to the possibility to allow multiple accesses with multiple frequencies.


Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1146
Author(s):  
Carlos Sánchez-Azqueta ◽  
Erick Guerrero ◽  
Cecilia Gimeno ◽  
Santiago Celma

This work presents a reconfigurable RF converter for DVB-T television applications using triple-play over GPON. The system takes the DVB-T input, a wavelength division multiplexing (WDM) signal with spectral inversion in the range from 47 M Hz –1000 M Hz , up-converts its frequency to the band-pass of a highly selective surface-acoustic wave (SAW) filter centered at 1 . 3 G Hz , and then down-converts it so that it is compatible with the antenna input of conventional television sets. The designed RF converter incorporates two pairs of frequency synthesizer and mixer, based, respectively, on an integer-N phase-locked loop (PLL) with two LC-tank VCOs with 128 coarse tuning bands in the range from 1.35 G Hz –2.7 G Hz , and a double-balanced Gilbert cell, modified for better impedance matching and improved linearity. It is fed with regulated supplies compensated in temperature and programmed by an I 2 C interface operating on five 16-bit registers. This work presents the experimental characterization of the whole system plus selected cells for stand-alone testing, which have been fabricated in a 0 . 18 m CMOS process.


Author(s):  
Haijun Liu ◽  
Xingsheng Xu ◽  
Luhong Mao ◽  
Peng Gao ◽  
Hongda Chen

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