A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver

Author(s):  
Kazuo Matsukawa ◽  
Yosuke Mitani ◽  
Masao Takayama ◽  
Koji Obata ◽  
Yusuke Tokunaga ◽  
...  
Author(s):  
Koji OBATA ◽  
Kazuo MATSUKAWA ◽  
Yosuke MITANI ◽  
Masao TAKAYAMA ◽  
Yusuke TOKUNAGA ◽  
...  

2017 ◽  
Vol 27 (03) ◽  
pp. 1850044 ◽  
Author(s):  
Alireza Shamsi ◽  
Esmaeil Najafi Aghdam

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.


Author(s):  
Astria Nur Irfansyah ◽  
Long Pham ◽  
Andrew Nicholson ◽  
Torsten Lehmann ◽  
Julian Jenkins ◽  
...  

Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao

Abstract A brief presents a 2nd order continuous-time delta-sigma modulator (CT-DSM) using a low pass filter to reduce the slew rate requirement of the output swing of the first integrator. By adding the low pass filter, the desired transfer function of the CT-DSM is altered. Thus a feed-forward based compensation circuit is introduced to transform the altered transfer function to the original condition. The CT-DSM is designed with a bandwidth of 100 Hz to satisfy the requirement of photoplethysmogram (PPG) detection. The CT-DSM is simulated using CMOS 180 nm technology with the layout area 460 μm × 460 μm. The circuit uses a 1.8 V supply voltage and consumes 35.61 μW. The signal-to-noise ratio of the CT-DSM is 101.2 dB, while the SFDR is 99.1 dB.


Sign in / Sign up

Export Citation Format

Share Document