Parity preserving logic based fault tolerant reversible ALU

Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.

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Improved Fault Tolerant ALU Architecture

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.f8131.088619 ◽

2019 ◽

Vol 8 (6) ◽

pp. 1477-1484

Keyword(s):

Design Automation ◽

Driving Force ◽

Fault Tolerant ◽

Quantum Cost ◽

Verilog Hdl ◽

Reversible Computing ◽

Computer Scientists ◽

Smart Computing ◽

Reversible Alu ◽

Ic Technology

The birth to IC technology by Moore became driving force behind civilization and it spent almost 45 years successfully without any scruple in mind. It affected life of a mankind and brought pivotal moment in civilization. Now technology is hitting atomic levels and soon limits will be touched. Therefore time has come to rethink for an alternative solution that may slow down exponential rate demonstrated by Moore. Reversible computing is emerging as a superior technology and soon will be future of all smart computing applications. Although renowned physicists and computer scientists have investigated remarkable results in reversible logic based arithmetic logic unit (ALU) designing still research in the field of reversible ALU with add on fault tolerance is under progress and there is scope of further optimization. This paper aims in investigation of improved fault tolerant ALU architecture using parity preserving fault tolerant reversible adder (FTRA), double Feynman and conservative Fredkin gates. Performance evaluation of proposed architecture is done in respect of functionality, garbage lines, ancillary lines, quantum cost and number of gates. The quantum cost of all gates is verified using RCViewer+ tool. The proposed architecture is coded in Verilog HDL, Synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2.

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A Novel Design and Evaluation of a Low Power Efficient Fault-Tolerant Reversible ALU Using QCA: Applications of Nanoelectronics

10.21203/rs.3.rs-182881/v1 ◽

2021 ◽

Author(s):

Mary Swarna Latha Gade ◽

Rooban S

Keyword(s):

Low Power ◽

High Speed ◽

Fault Tolerant ◽

Logic Gates ◽

Reversible Logic ◽

Functional Verification ◽

Logical Operations ◽

Arithmetic Logic Unit ◽

Reversible Alu ◽

Logic Unit

Abstract Reversible logic based on Quantum-dot Cellular Automata (QCA) is the most requirement for achieving nano-scale architecture that promises significantly high device integration density, high-speed calculation, and low power consumption. The arithmetic logic unit (ALU) is the significant component of a processor for processing and computing. The primary objective of this work is to develop a multi-layer fault-tolerant arithmetic logic unit using reversible logic in QCA technology. Additionally, the reversible ALU has divided into arithmetic (RAU) and a logic unit (RLU). A reversible 2:1 MUX using the Fredkin gate has been implemented to select either the arithmetic or logical operations. Besides, to improve the efficiency of arithmetic operations, a novel QCA reversible full adder is implemented. To build the ALU, fault-tolerant reversible logic gates are used. The proposed reversible multilayer QCA ALU is designed to carry out eight arithmetic and sixteen logical operations with a minimum number of gates, constant inputs, and garbage outputs compared to the existing works. The functional verification and simulation of the presented circuits are assessed by the QCADesigner tool.

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