To implement positive feedback adiabatic logic (PFAL)—NAND technique on low power Zigbee applications for processor applications

2020 ◽  
Vol 76 ◽  
pp. 102856
Author(s):  
K. Parthiban ◽  
S. Sasikumar
Keyword(s):  
Low Power ◽  
Positive Feedback ◽  
Adiabatic Logic

scholarly journals Energy Efficient Digital Circuit Based on Self Cascoding Positive Feedback Adiabatic Logic for Low Power VLSI Design

2019 ◽  
Vol 8 (2S11) ◽  
pp. 950-954
Keyword(s):  
Low Power ◽  
Positive Feedback ◽  
Vlsi Design ◽  
Digital Circuit ◽  
Operating Frequency ◽  
Threshold Region ◽  
Clock Frequency ◽  
Ultra Low Power ◽  
Prime Concern ◽  
Adiabatic Logic

Emphasis in VLSI design has shifted from high speed to low power due to the proliferation of portable electronic systems. The continuing decrease in feature size and corresponding increase in chip density and operating frequency have made power consumption as a prime concern in VLSI design. For ultra low power applications, the idea of self cascode positive feedback adiabatic logic (SC-PFAL) has reported as a promising candidate to reduce power dissipation at low operating frequency. To enhance the energy efficiency of the logic circuits, self cascoding of transistor is applied to charge recovery logic working in sub-threshold region. Based on this proposed technique, we design a basic MOS digital library cell. Simulation results are found using 70nm technology model file available from predictive technologies. At low clock frequency, the proposed logic i.e. SC-PFAL has significant improvement in terms of energy consumption than original PFAL.

Evolutionary Approach of Adiabatic Logic Design on Low Power Solution �A Robust Survey

2012 ◽  
Vol 1 (2) ◽  
pp. 36-49
Author(s):  
A. Kishore Kumar ◽  
D. Somasundareswari ◽  
V. Duraisamy ◽  
T. Shunbaga Pradeepa
Keyword(s):  
Low Power ◽  
Evolutionary Approach ◽  
Logic Design ◽  
Adiabatic Logic
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