A 0.450 µW 125 ppm/°C PVT compensated 100nA current reference in 0.18 µm CMOS technology

Author(s):  
R. Sanjay ◽  
Vipul Jha ◽  
B Venkataramani
2017 ◽  
Vol 2 (1) ◽  
pp. 1-4
Author(s):  
Dinesh Kushwaha ◽  
D. K. Mishra

This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub-threshold –operated power-aware large-scale integration


Author(s):  
E.M. Camacho-Galeano ◽  
C. Galup-Montoro ◽  
M.C. Schneider

Author(s):  
Mark Arvie C. Aguinaga ◽  
Mervin T. Desengano ◽  
Kier Joshua M. Dimaunahan ◽  
Frince Aristotle M. Pinpin ◽  
Francis A. Malabanan ◽  
...  

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-41-C4-44
Author(s):  
G. J.T. DAVIDS ◽  
P. B. HARTOG ◽  
J. W. SLOTBOOM ◽  
G. STREUTKER ◽  
A. G. van der SIJDE ◽  
...  
Keyword(s):  

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-13-C4-22
Author(s):  
F. NEPPL ◽  
H.-J. PFLEIDERER
Keyword(s):  

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-421-C4-424 ◽  
Author(s):  
A. STRABONI ◽  
M. BERENGUER ◽  
B. VUILLERMOZ ◽  
P. DEBENEST ◽  
A. VERNA ◽  
...  

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