Test-data volume and test execution times are both costly commodities. To reduce the cost of test, previous studies have used test-data compression techniques on system-level to reduce the test-data volume or employed test architecture design for module-based SOCs to enable test schedules with low test execution time. Research on combining the two approaches is lacking. Therefore, this chapter studies how core-level test-data compression can be combined with test architecture design to reduce test cost further. The study is conducted in three steps. The first step analyzes how the TAM width influences three test-data compression techniques, namely Selective Encoding, Vector Repeat and the combination of the two. The second step investigates in what order to consider test architecture and test-data compression in the SOC design process to best reduce test cost. It is observed that test architecture design and test-data compression-technique selection should be performed in an integrated process. The third step presents a novel approach to integrate test-data compression-technique selection in the test architecture design process. Experiments on benchmarks with realistic cores show that the integrated approach achieves up to 32% reduction in test cost (7.8% on average) compared to non-integrated test architecture design and test-data compression technique selection.
SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects