A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology

Author(s):  
F. Tobajas ◽  
R. Esper-Chain ◽  
R. Regidor ◽  
O. Santana ◽  
R. Sarmiento
2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.


2013 ◽  
Vol 34 (9) ◽  
pp. 095002
Author(s):  
Kai Tang ◽  
Qiao Meng ◽  
Zhigong Wang ◽  
Yi Zhang ◽  
Kuai Yin ◽  
...  

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