A low power programmable gain high PAE K-/Ka-band stacked amplifier in 0.18 µm SiGe BiCMOS technology

Author(s):  
Thangarasu Bharatha Kumar ◽  
Kaixue Ma ◽  
Kiat Seng Yeo
Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1608
Author(s):  
Kai Men ◽  
Hang Liu ◽  
Kiat Seng Yeo

In this work, the design of a novel Ka-band miniaturized bandpass filter with broad bandwidth is demonstrated by using inversely coupled U-shaped transmission lines. In the proposed filter, two transmission zeros can be generated within a cascaded U-shaped structure and it can also be proven that, by inversely coupling two stacked U-shaped transmission lines, the notch frequency at the upper stopband can be shifted to a lower frequency, which results in a smaller chip size. The key parameters affecting the performance of the proposed filter are investigated in detail with the effective lumped-element circuit illustrated. Fabricated in a 0.13-μm SiGe BiCMOS process, the proposed filter achieves an insertion loss of 3.6 dB at a frequency of 28.75 GHz and the measured bandwidth is from 20.75 GHz to 41 GHz. The return loss is better than −10 dB from 20.5 GHz to 39 GHz. The lower transmission zero is located at 11.75 GHz with a suppression of 54 dB while the upper transmission zero is around 67 GHz with an attenuation of 34.6 dB. The measurement agrees very well with the simulation results and the overall chip size of the proposed filter is 176 × 269 μm2.


2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.


Frequenz ◽  
2017 ◽  
Vol 71 (3-4) ◽  
Author(s):  
Xuan-Quang Du ◽  
Anselm Knobloch ◽  
Markus Grözing ◽  
Matthias Buck ◽  
Manfred Berroth

AbstractThis paper presents the analysis and the design of a fully-differential digital programmable gain amplifier (PGA) in a 0.13 µm BiCMOS technology. The PGA has a gain control range of 31 dB with 1 dB gain step size and consumes 284 mW from a 3.6 V power supply. At a maximum gain of 25 dB, the PGA exhibits a 3-dB bandwidth of 10.1 GHz. The measured gain error for all 32 possible gain settings is between –0.19/+0.46 dB at 1 GHz. Up to 13 GHz the third harmonic distortion


Sign in / Sign up

Export Citation Format

Share Document