Relaxed equivalence checking: a new challenge in logic synthesis

2017 ◽  
Author(s):  
Zdenek Vasicek
Keyword(s):  
Logic Synthesis ◽  
Equivalence Checking

Using Logic Synthesis and Circuit Reasoning for Equivalence Checking

2011 ◽  
Vol 201-203 ◽  
pp. 836-840
Author(s):  
Quan Run Fan ◽  
Feng Pan ◽  
Xin Dong Duan
Keyword(s):  
Logic Synthesis ◽  
Experimental Result ◽  
Equivalence Checking ◽  
Structure Information ◽  
Preliminary Experimental Result ◽  
Sat Solver

The existing SAT based algorithms combines two circuits into a miter, and then convert the miter into a CNF formula. After that, a SAT solver is invoked to check the satisfiability of the CNF formula. However, when a miter is converted into CNF formula, the structure information of the circuit is lost. Therefore,we are motivated to solve the problem of miter satisfiability using circuit reasoning. We use logic synthesis first to simplify the circuit, and then use a backtracking method to check the satisfiability of the miter. The preliminary experimental result sindicate that our approach is efficient.

scholarly journals Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs

VLSI Design ◽  
2002 ◽  
Vol 14 (1) ◽  
pp. 53-64 ◽  
Author(s):  
M. A. Thornton ◽  
R. Drechsler ◽  
W. Günther
Keyword(s):  
Boolean Functions ◽  
Logic Synthesis ◽  
Logic Circuit ◽  
Experimental Results ◽  
Equivalence Checking ◽  
Spectral Coefficients

A probabilistic equivalence checking method is developed based on the use of partial Haar Spectral Diagrams (HSDs). Partial HSDs are defined and used to represent a subset of Haar spectral coefficients for two Boolean functions. The resulting coefficients are then used to compute and to iteratively refine the probability that two functions are equivalent. This problem has applications in both logic synthesis and verification. The method described here can be useful for the case where two candidate functions require extreme amounts of memory for a complete BDD representation. Experimental results are provided to validate the effectiveness of this approach.

Algorithm of Optimizing Quantum Reversible Logic Synthesis

2009 ◽  
Vol 20 (9) ◽  
pp. 2332-2343
Author(s):  
Zhi-Qiang LI ◽  
Wen-Qian LI ◽  
Han-Wu CHEN
Keyword(s):  
Logic Synthesis ◽  
Reversible Logic ◽  
Reversible Logic Synthesis

Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation

2019 ◽  
Vol 12 (1) ◽  
pp. 30-39 ◽  
Author(s):  
Apangshu Das ◽  
Sambhu Nath Pradhan
Keyword(s):  
Integrated Circuits ◽  
Power Density ◽  
Logic Synthesis ◽  
Programmable Logic Arrays ◽  
Power Switching ◽  
Nsga Ii ◽  
Multi Level ◽  
Search Approach ◽  
Efficient Power ◽  
The Impact

Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at the two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to be consider, because power-density directly converges to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to excessive overheating. Methods: This work demonstrates the impact of efficient power density based logic synthesis (in the form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel realization) for the reduction of temperature. Two-level PLA optimization using output polarity selection is considered first and compared with other existing techniques and then And-Invert Graphs (AIG) based multi-level realization has been considered to overcome the redundant solution generated in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting, refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of PLA sub-functions for its optimal realization. Results: Best power density based solution saves up to 8.29% power density compared to ‘espresso – dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are obtained with respect to ‘espresso’ based solution using NSGA-II. Conclusion: Suitable output polarity realized circuit is converted into multi-level AIG structure and synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the increase in power density, the temperature of a particular circuit is also increases.

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