The TEM cell test method (for road vehicle electronic components)

Author(s):  
Bimbaum
1977 ◽  
Vol 10 (1) ◽  
pp. 49-56
Author(s):  
C.G. Balachandran ◽  
K.O. Ballagh ◽  
T.A. Lister

1993 ◽  
Vol 115 (3) ◽  
pp. 233-239
Author(s):  
J. A. Owczarek

This paper describes a study of the process of deposition of RTV dispersion on electronic components placed on substrates. The objective was to develop a technique for the consistent manufacture of encapsulant coating of a desired thickness and extent. In addition, it was desired to obtain an understanding of the phenomenon of run-over, or wicking, of the RTV dispersion onto external leads of circuits being encapsulated, and of means to control it. In this paper physical properties of the RTV dispersion which influence the deposition process were determined using a novel drop test method. These properties allow building of a physical model of the deposition process, and its analysis. The results of drop tests show that the RTV dispersion behaves like a plastic “false body” material which possesses yield stress after a long rest, and which retains residual yield stress after shearing. Part I of this paper is concerned with building of the physical model of the encapsulant deposition process. It also deals with the derivation of an equation relating the wall shear stress to the encapsulant volumetric flow rate.


2019 ◽  
Vol 33 (31) ◽  
pp. 1950387
Author(s):  
Xiaofei Jia ◽  
Wenhao Chen ◽  
Bing Ding ◽  
Liang He

In recent years, with the development of mesoscopic physics and nanoelectronics, the research on noise and testing technology of electronic components has been developed. It is well known that noise can characterize the transmission characteristics of carriers in nanoscale electronic components. With the continuous shrinking of the device size, the carrier transport of nanoscale MOSFET devices has been gradually transformed from the traditional drift-diffusion to become the quasi-ballistic or ballistic transport, and its current noise contains granular and thermal noise. The paper by Jeon et al. [The first observation of shot noise characteristics in 10-nm scale MOSFETs, in Proc. 2009 Symp. VLSI Technology (IEEE, Honolulu, 2009), pp. 48–49] presents the variation relation of 20 nm MOSFET current noise with source–drain current and voltage, and its current noise characteristic is between thermal noise and shot noise, so 20 nm MOSFET current noise is shot noise and thermal noise. The paper by Navid et al. [J. Appl. Phys. 101 (2007) 124501] shows through simulation that the 60 nm MOSFET current noise is suppressed shot noise and thermal noise. At present, the current noise has seriously affected the basic performance of the device, thus the circuit cannot work normally. Therefore, it is necessary to study the generation mechanism and characteristics of current noise in electronic components so as to suppress device noise, which can not only realize the reduction of device noise, but also play a positive role in the work-efficiency, life-span and reliability of electronic components.


2005 ◽  
Vol 297-300 ◽  
pp. 893-898
Author(s):  
Seung Mo Kim ◽  
Eun Sook Shon ◽  
Yoon Hyun Ka ◽  
Yong Joon Kim ◽  
Jin Young Kim ◽  
...  

Cyclic bend test and drop test were carried out as a second level reliability test method in order to characterize the joint performance between electronic components and board. Two types of package substrates were used for the test. The one was NiAu plated, and the other one was organic solderability preservatives (OSP) finished. Drop test was done in accordance with JEDEC standard test method [1]. Drop impact and duration time was 1,500G and 0.5ms, respectively. Cyclic bend test was performed with Amkor internal specification because there is no international standard for the test. The Amkor internal specification was edited based on the IPC/JEDEC specification [2]. Board deflection and cyclic frequency was 3mm and 1Hz, respectively. NiAu substrate showed better mean life performance about by 30% in cyclic bend test. OSP substrate showed the same or better failure rate performance in drop test. Typical solder joint failures and intermetalic crack were found by failure analysis.


2013 ◽  
Vol 477-478 ◽  
pp. 509-513
Author(s):  
Li Zhang Yao ◽  
Deng Feng Sang ◽  
Lin Wang Su ◽  
De Yin Tan

The O-cell test method which was applied on the pile load testing was introduced, including the basic principle, test device and test technique. Based on the project of offshore structure in Malaysia, the O-cell test was performed on the long rock socket bored pile. The bearing behavior and load transfer characteristics were analyzed. The shaft friction in the rock played an important role in the pile shaft friction. In some long rock socket pile, The O-cell method cant test the ultimate capacity of some long rock socket pile.


2021 ◽  
Author(s):  
Ledong Chen ◽  
Jianfei Wu ◽  
Hongli Zhang ◽  
Yifei Zheng ◽  
Jianyu Wu
Keyword(s):  

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