Analysis and Design of a 50-GHz 2:1 CMOS CML Static Frequency Divider Based on LC-tank

Author(s):  
Yuan Mo ◽  
Efstratios Skafidas ◽  
Rob Evans ◽  
Iven Mareels
2009 ◽  
Vol 51 (8) ◽  
pp. 1970-1973 ◽  
Author(s):  
Sheng-Lyang Jang ◽  
Jyun-Yan Wun ◽  
Cheng-Chen Liu ◽  
Miin-Horng Juang

2017 ◽  
Vol 27 (03) ◽  
pp. 1850039 ◽  
Author(s):  
Yue Wu ◽  
Hongliang Lv ◽  
Yuming Zhang ◽  
Yimen Zhang ◽  
Shaojun Li

A modified divide-by-2 regenerative frequency divider (RFD) is presented in this paper. The effects of modified active loads on the bandwidth of RFD are demonstrated and analyzed in detail by introducing the equivalent circuit using [Formula: see text] model. Using the transimpedance amplifier structure with resistive shunt–shunt feedback and shunt-peaked inductor as the active loads of the generative frequency divider, the loop bandwidth and the loop gain can be increased at higher frequencies to extend the bandwidth. Based on the theoretical analysis and design methodology, an RFD with improved active loads is designed and fabricated in 1[Formula: see text][Formula: see text]m GaAs heterojunction bipolar transistor technology with a total chip area of 0.83[Formula: see text]mm[Formula: see text][Formula: see text][Formula: see text]0.75[Formula: see text]mm. The measured phase noise at the divider output is less than [Formula: see text]110[Formula: see text]dBc/Hz with 100[Formula: see text]kHz offset and is [Formula: see text]127.6[Formula: see text]dBc/Hz with 1[Formula: see text]MHz offset. The operation frequency range is from 10 to 26[Formula: see text]GHz. The power consumption of the divider core is 166.44[Formula: see text]mW, and the frequency bandwidth is 16[Formula: see text]GHz at a supply voltage of [Formula: see text]6[Formula: see text]V.


2008 ◽  
Vol 18 (8) ◽  
pp. 560-562 ◽  
Author(s):  
S.-L. Jang ◽  
S.-H. Huang ◽  
C.-F. Lee ◽  
M.-H. Juang

2008 ◽  
Vol 50 (3) ◽  
pp. 592-595 ◽  
Author(s):  
S.-L. Jang ◽  
Fei-Hung Chen ◽  
Jhin-Fang Huang
Keyword(s):  

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