PCIe Gen-5 Design Challenges of High-Speed Servers

Author(s):  
Mallikarjun Vasa ◽  
Chun-Lin Liao ◽  
Sanjay Kumar ◽  
Ching-Huei Chen ◽  
Bhyrav Mutnury
Keyword(s):  
Author(s):  
Selwan K. Ibrahim ◽  
John A. O’Dowd ◽  
Raymond McCue ◽  
Arthur Honniball ◽  
Martin Farnan

2008 ◽  
Vol 17 (01) ◽  
pp. 1-13 ◽  
Author(s):  
HAMED AMINZADEH ◽  
REZA LOTFI

Optimization of power consumption is one of the main design challenges in today's low-power high-speed analog integrated circuits. In this paper, two popular techniques to stabilize two-stage operational amplifiers, namely, Miller and cascode compensations are compared from power efficiency point of view. To accomplish this, cascode-compensated topologies are basically analyzed to derive the required equations for the comparison. In the analysis, a new method to take into account the effect of transfer function zeros is proposed. By assuming that the zeros' magnitudes are fairly nondominant, the method increases the accuracy of the analyses. The relationships show that for the same specifications, cascode compensation is more power-efficient than Miller compensation, especially for heavy capacitive loads. This has been confirmed by SPICE simulations.


2010 ◽  
Vol 56 (2) ◽  
pp. 107-110 ◽  
Author(s):  
Adam Handzlik ◽  
Andrzej Jabłonski

Large Data Stream Processing - Embedded Systems Design Challenges The following paper describes an application of reconfigurable hardware architectures for processing of huge data streams. Radar, sonar and high speed internet networks are typical sources of data that require extreme computing power and resources to enable real time acquisition, processing and management. An approach to monitoring of real time multi-gigabit internet network has been described as a practical application of FPGA based board, designed for fast data processing.


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