A ring-VCO-based sub-sampling PLL CMOS circuit with −119 dBc/Hz phase noise and 0.73 ps jitter
Keyword(s):
2011 ◽
Vol 131
(8)
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pp. 1397-1402
Keyword(s):
2011 ◽
Vol 131
(3)
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pp. 507-513
2018 ◽
Vol 138
(5)
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pp. 192-197
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2012 ◽
Vol E95.C
(12)
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pp. 1846-1856
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2012 ◽
Vol E95.C
(6)
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pp. 1077-1085
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