A ring-VCO-based sub-sampling PLL CMOS circuit with −119 dBc/Hz phase noise and 0.73 ps jitter

Author(s):  
Kenta Sogo ◽  
Akihiro Toya ◽  
Takamaro Kikkawa
Keyword(s):  
2018 ◽  
Author(s):  
Nicola Da Dalt ◽  
Ali Sheikholeslami
Keyword(s):  

2012 ◽  
Vol E95.C (12) ◽  
pp. 1846-1856 ◽  
Author(s):  
Seyed Amir HASHEMI ◽  
Hassan GHAFOORIFARD ◽  
Abdolali ABDIPOUR

2012 ◽  
Vol E95.C (6) ◽  
pp. 1077-1085 ◽  
Author(s):  
Kosuke KATAYAMA ◽  
Mizuki MOTOYOSHI ◽  
Kyoya TAKANO ◽  
Ryuichi FUJIMOTO ◽  
Minoru FUJISHIMA

2013 ◽  
Vol E96.C (2) ◽  
pp. 241-244
Author(s):  
Ryuta YAMANAKA ◽  
Taka FUJITA ◽  
Hideyuki SOTOBAYASHI ◽  
Atsushi KANNO ◽  
Tetsuya KAWANISHI

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