Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

Controllable Synthesis of Pt Functionalized Black Phosphorus (BP) Nanocomposite for High Performance NOx Gas Sensor

Compared with bulk material-based sensors, functional sensors fabricated with nanomaterials have many advantages, such as high sensitivity, multifunctional integration, low power-dissipation, and low cost. Black phosphorus (BP) is a two-dimensional (2D) crystal material, which has a higher molecular adsorption energy, tunable direct band gap, high carrier mobility, ambipolar characteristics, and high current on/off ratio. In this paper, BP bulk was ground into powder, and then the powder was dispersed in dimethylformamide (DMF) to obtain two-dimensional BP nanosheets solution. Afterwards, the black phosphorus nanosheets and H2PtCl6 solution were mixed to obtain the Pt functionalized BP nanocomposite by one-step reduction method. Pt nanoparticles were dispersed on the surface of BP nanosheets with highly uniform size. The Pt functionalized BP nanocomposite exhibited a high response of 2.19 to 10 ppm NOx in a short period of 1.93 s at room temperature. The detection limit was as low as 30 ppb. The Pt functionalized BP nanocomposite will be useful for precise detection of NOx.

CMOS Implementation of 5T SRAM with Low Power Dissipation

SRAM is a very fast memory with low power consumption. The main objective of this work is to perform a 64-digit SRAM with 90 nm innovation. Execution depended on a granular perspective. SRAM's base module is similar to an N-MOS inverter, flip-flop, and semiconductor. We design this module according to the configuration rule of the ? format. Using Harvard technology, SRAM can easily retrieve information from memory. To create advanced rational circuits, it is important to see how an SRAM is assembled and how it works. The bottom line is that with 0.12 micron 90nm technology, we are developing a 5T SRAM and we can read and write. It is a fundamental part of a computer's central processing unit. RAM is a building block made up of several circuits. The 64-bit SRAM reader was developed with MICROWIND and DSCH2. With the MICROWIND program, the developer can design and simulate an integrated circuit at the physical description level. DSCH2 allows switching of digital logic design.

Reliability and Power Analysis of FinFET Based SRAM

Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM files in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

A custom HW design of a Fully Convolutional Neural Network (FCN) is presented in this paper to implement an embeddable Human Posture Recognition (HPR) system capable of very high accuracy both for laying and sitting posture recognition. The FCN exploits a new base-2 quantization scheme for weight and binarized activations to meet the optimal trade-off between low power dissipation, a very reduced set of instantiated physical resources and state-of-the-art accuracy to classify human postures. By using a limited number of pressure sensors only, the optimized HW implementation allows keeping the computation close to the data sources according to the edge computing paradigm and enables the design of embedded HP systems. The FCN can be simply reconfigured to be used for laying and sitting posture recognition. Tested on a public dataset for in-bed posture classification, the proposed FCN obtains a mean accuracy value of 96.77% to recognize 17 different postures, while a small custom dataset has been used for training and testing for sitting posture recognition, where the FCN achieves 98.88% accuracy to recognize eight positions. The FCN has been prototyped on a Xilinx Artix 7 FPGA where it exhibits a dynamic power dissipation lower than 11 mW and 7 mW for laying and sitting posture recognition, respectively, and a maximum operation frequency of 47.64 MHz and 26.6 MHz, corresponding to an Output Data Rate (ODR) of the sensors of 16.50 kHz and 9.13 kHz, respectively. Furthermore, synthesis results with a CMOS 130 nm technology have been reported, to give an estimation about the possibility of an in-sensor circuital implementation.

A Survey on Placement and Routing for Field-Coupled Nanocomputing

CMOS technology is reaching power, thermal, and physical limits at an alarming pace. As a response, post-silicon research investigates alternative technologies to perform computation. Field-Coupled Nanocomputing (FCN) presents low power dissipation, high frequencies, and room temperature operation. Nevertheless, FCN imposes several challenges in the development of efficient and scalable CAD tools. The placement and routing step is especially tricky in FCN compared to CMOS because of synchronization issues inherent to these technologies, such as path balancing and reconvergent paths. In this work, we survey the state-of-art of placement and routing algorithms for FCN. We describe the most recent FCN placement and routing algorithms, highlighting their limitations and, finally, presenting future work directions.

Optimizing DODAG Build with RPL Protocol

In the lossy wireless network routing system based on RPL technology, an improved DODAG construction optimization scheme is proposed for sensor nodes with low-power dissipation in the interference environment. If a node discovers that all paths between it and its neighbors have failed, the node reset action begins. Once the node reset is complete, the DODAG system build process is resumed. This prevents the DODAG root from initiating a global fix by incrementing the DODAG VersionNumer to produce a new version of the DODAG in a disruptive environment. The power loss caused by this global repair operation is avoided. The performance of DODAG in interference environment is enhanced, and the data retransmission rate is reduced.