Performance Improvement in single-gate organic transistors with contacts at top and bottom: Additional p + region insertion near source and drain

This research explores performance attributes of bottom gate top contact (BGTC) and bottom gate bottom contact (BGBC) organic thin film transistors (OTFT). To upgrade the performance characteristics, a region of 5nm with high concentration of carrier is tallied neighboring contacts. The drain current for BGTC is –18.6μ A as compared to –5.1μ A of BGBC transistor. Also, it is established that the innate attributes of BGTC are better than those of their counterparts, which is typically considered because of the inadequate contact attributes and mediocre semiconductor quality of BGBC OTFT. The analysis showed that upon varying the length of the channel ranging from 5μm to 40μm, there was a significant change in the drain current of BGTC and BGBC devices. For the same values of V GS and V DS (0V to –5V) where drain current in BGTC structure varied from –129.86μ A to –13.69μ A, whereas for their counterparts it ranged from –37.10μ A to –3.76μ A for channel length equal to 5μ m and 40μ m respectively. Also, with the varying doping strength ranging from 1012 cm–3 to 1016 cm–3 for BGBC device, drain current varied from –2.15μ A to –18.52μ A for BGTC whereas for BGBC it varied from –0.19μ A to –7.09μ A keeping V GS and V DS –5 V, yielding that upon varying the doping strength, where for BGTC I D changed by a factor of 8.6, the BGBC device showed a considerable change by a factor of 37.3. Likewise, mobility, threshold voltage, sub-threshold swing and transconductance also showing better performance with the P + insertion. These variations in the innate attributes are primarily due to the deficiency of carriers at the interface of source and channel, leading to a greater drop in the potential, which is more prominent for the bottom gate bottom contact devices.

Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure

We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 104. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.