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Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults
2018 IEEE East-West Design & Test Symposium (EWDTS)
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10.1109/ewdts.2018.8524628
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2018
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Author(s):
S. Ostanin
◽
V. Andreeva
◽
N. Butorina
◽
D. Tretyakov
Keyword(s):
Network Design
◽
Fault Tolerant
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Delay Faults
◽
Path Delay
◽
Path Delay Faults
Download Full-text
Related Documents
Cited By
References
Self-checking synchronous FSM network design for path delay faults
2017 IEEE East-West Design & Test Symposium (EWDTS)
◽
10.1109/ewdts.2017.8110129
◽
2017
◽
Cited By ~ 6
Author(s):
S. Ostanin
Keyword(s):
Network Design
◽
Delay Faults
◽
Path Delay
◽
Path Delay Faults
Download Full-text
A Fault-tolerant Sequential Circuit Design for Stuck-at Faults and Path Delay Faults
Vestnik Tomskogo gosudarstvennogo universiteta Upravlenie vychislitel naya tekhnika i informatika
◽
10.17223/19988605/41/8
◽
2017
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pp. 61-68
Author(s):
Anjela Yurievna Matrosova
◽
◽
Sergey Alexandrovich Ostanin
◽
Irina Evgenievna Kirienko
◽
Ekaterina Alexandrovna Nikolaeva
Keyword(s):
Circuit Design
◽
Fault Tolerant
◽
Delay Faults
◽
Path Delay
◽
Path Delay Faults
◽
Sequential Circuit
Download Full-text
Parallel pattern fault simulation of path delay faults
Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89
◽
10.1145/74382.74442
◽
1989
◽
Cited By ~ 46
Author(s):
M. Schulz
◽
F. Fink
◽
K. Fuchs
Keyword(s):
Fault Simulation
◽
Delay Faults
◽
Path Delay
◽
Path Delay Faults
◽
Parallel Pattern
Download Full-text
A satisfiability-based test generator for path delay faults in combinational circuits
33rd Design Automation Conference Proceedings, 1996
◽
10.1109/dac.1996.545574
◽
2005
◽
Cited By ~ 30
Author(s):
Chih-Ang Chen
◽
S.K. Gupta
Keyword(s):
Delay Faults
◽
Path Delay
◽
Combinational Circuits
◽
Path Delay Faults
Download Full-text
Fast test pattern generation for all path delay faults considering various test classes
Proceedings ETC 93 Third European Test Conference
◽
10.1109/etc.1993.246529
◽
2002
◽
Cited By ~ 15
Author(s):
K. Fuchs
◽
H.C. Wittmann
◽
K.J. Antreich
Keyword(s):
Test Pattern
◽
Pattern Generation
◽
Test Pattern Generation
◽
Delay Faults
◽
Path Delay
◽
Path Delay Faults
Download Full-text
Functional-based ATPG for path delay faults
2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)
◽
10.1109/ssmsd.2000.836465
◽
2002
◽
Cited By ~ 1
Author(s):
M. Michael
◽
S. Tragoudas
Keyword(s):
Delay Faults
◽
Path Delay
◽
Path Delay Faults
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Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts
2006 IEEE/ACM International Conference on Computer Aided Design
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10.1109/iccad.2006.320072
◽
2006
◽
Author(s):
Shun-yen Lu
◽
Pei-ying Hsieh
◽
Jing-jia Liou
Keyword(s):
Critical Path
◽
Delay Faults
◽
Path Delay
◽
Path Delay Faults
◽
Linear Structures
◽
Critical Path Delay
Download Full-text
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/43.476581
◽
1995
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Vol 14
(12)
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pp. 1505-1515
◽
Cited By ~ 30
Author(s):
I. Pomeranz
◽
S.M. Reddy
◽
P. Uppaluri
Keyword(s):
Test Generation
◽
Delay Faults
◽
Path Delay
◽
Combinational Circuits
◽
Path Delay Faults
Download Full-text
Deterministic broadside test generation for transition path delay faults
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10
◽
10.1145/1785481.1785514
◽
2010
◽
Cited By ~ 1
Author(s):
Bo Yao
◽
Irith Pomeranz
◽
Sudhakar M. Reddy
Keyword(s):
Test Generation
◽
Delay Faults
◽
Path Delay
◽
Path Delay Faults
◽
Transition Path
Download Full-text
Identification of critical primitive path delay faults without any path enumeration
2010 28th VLSI Test Symposium (VTS)
◽
10.1109/vts.2010.5469629
◽
2010
◽
Cited By ~ 7
Author(s):
Kyriakos Christou
◽
Maria K. Michael
◽
Stelios Neophytou
Keyword(s):
Delay Faults
◽
Path Delay
◽
Path Delay Faults
Download Full-text
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