Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems

2021 ◽  
Author(s):  
A Bernard Rayappa ◽  
TVP Sundararajan
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Viterbi Algorithm ◽  
Model Performance ◽  
Cmos Technology ◽  
High Rate ◽  
Viterbi Decoder ◽  
Hardware Complexity ◽  
Large Power ◽  
Constraint Length

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to a large number of Trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add-Compare-Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of the Viterbi decoder mainly depends on its efficient implementation of the ACS module, in the literature, several methods are presented for the implementation of ACS for the Viterbi decoder. The methods based on Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer, Shannon’s decomposition circuits, body-biased pseudo-NMOS logic and Quasi Delay Insensitive (QDI) timing model performance is analyzed. The methods are implemented using CMOS technology. In this paper, FinFET and CNTFET-based ACS implementation is performed. From the analysis, it has been found that the Carbon Nanotube-based implementation is better in performance when compared to the CMOS and FinFET technology. The proposed QDI model and retiming circuits for ACS block operate above 1[Formula: see text]GHz with high driving current and low power.

scholarly journals Design and VLSI Implementation of a Reduced-Complexity Sorted QR Decomposition for High-Speed MIMO Systems

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1657
Author(s):  
Lu Sun ◽  
Bin Wu ◽  
Tianchun Ye
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Mimo Systems ◽  
Multiple Input Multiple Output ◽  
Cmos Technology ◽  
Qr Decomposition ◽  
Time Sharing ◽  
Hardware Complexity ◽  
Givens Rotation ◽  
Hardware Efficiency

In this article, a low-complexity and high-throughput sorted QR decomposition (SQRD) for multiple-input multiple-output (MIMO) detectors is presented. To reduce the heavy hardware overhead of SQRD, we propose an efficient SQRD algorithm based on a novel modified real-value decomposition (RVD). Compared to the latest study, the proposed SQRD algorithm can save the computational complexity by more than 44.7% with similar bit error rate (BER) performance. Furthermore, a corresponding deeply pipelined hardware architecture implemented with the coordinate rotation digital computer (CORDIC)-based Givens rotation (GR) is designed. In the design, we propose a time-sharing Givens rotation structure utilizing CORDIC modules in idle state to share the concurrent GR operations of other CORDIC modules, which can further reduce hardware complexity and improve hardware efficiency. The proposed SQRD processor is implemented in SMIC 55-nm CMOS technology, which processes 62.5 M SQRD per second at a 250-MHz operating frequency with only 176.5 kilo-gates. Compared to related studies, the proposed design has the best normalized hardware efficiency and achieves a 6-Gbps MIMO data rate which can support current high-speed wireless communication systems such as IEEE 802.11ax.

Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA

2014 ◽  
Vol 24 (02) ◽  
pp. 1550026 ◽  
Author(s):  
Chang-Kun Yao ◽  
Yun-Ching Tang ◽  
Hongchin Lin
Keyword(s):  
Energy Efficient ◽  
Communication Systems ◽  
Average Power ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Hardware Complexity ◽  
Chip Area ◽  
Ldpc Decoder ◽  
Area Efficient

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

scholarly journals An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
T. Kalavathi Devi ◽  
Sakthivel Palaniappan
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Forward Error Correction ◽  
Vlsi Architecture ◽  
Convolutional Codes ◽  
Viterbi Decoder ◽  
Asynchronous Design

Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

scholarly journals DESIGN OF TCM DECODERS USING OPTIMIZED VITERBI DECODER

2015 ◽  
pp. 233-237
Author(s):  
D. KOKILANAYAKI
Keyword(s):  
Power Consumption ◽  
Viterbi Algorithm ◽  
Digital Communication ◽  
Error Correcting Codes ◽  
Viterbi Decoder ◽  
Hardware Complexity ◽  
Decoding Algorithm ◽  
Clock Speed ◽  
Exponential Increase ◽  
Forward Error

The use of forward error correcting codes in the digital communication is used to overcome the data corruptions. Although widely-used, the most popular communications decoding algorithm, the Viterbi algorithm, requires an exponential increase in hardware complexity to achieve greater decode accuracy. The Viterbi decoder that forms the dominant module of TCM decoders are responsible for the overall power consumption. We have analyzed the original T-algorithm with that of the precomputation architecture’s of the T-algorithm. The T-algorithm reduces the complexity of the original viterbi algorithm and reduces the power consumption by 70%.This can be done with the reduction in the negligible clock speed.

scholarly journals Verilog based efficient convolution encoder and viterbi decoder

2019 ◽  
Vol 8 (1) ◽  
pp. 75
Author(s):  
Md. Abdul Rawoof ◽  
Umasankar Ch. ◽  
D. Naresh Kumar ◽  
D. Khalandar Basha ◽  
N. Madhur
Keyword(s):  
Error Correction ◽  
Communication Systems ◽  
Viterbi Algorithm ◽  
Data Communication ◽  
Vital Role ◽  
Redundant Information ◽  
Viterbi Decoder ◽  
Correction Technique ◽  
Source Data ◽  
Digital Communication Systems

In the<strong><em> </em></strong>today’s<strong><em> </em></strong>digital communication Systems,<strong><em> </em></strong>transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.

scholarly journals Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine

2013 ◽  
Vol 84 (2) ◽  
pp. 24-27
Author(s):  
A. Mallaiah ◽  
K. Lakshmi Narayana ◽  
A. Jaya Lakshmi
Keyword(s):  
Low Power ◽  
Viterbi Decoder ◽  
Constraint Length

scholarly journals FPGA Implementation of Convolutional Encoder And Hard Decision Viterbi Decoder

2016 ◽  
pp. 126-130
Author(s):  
J. Tulasi ◽  
T.Venkata Lakshmi ◽  
M. Kamaraju
Keyword(s):  
Communication Systems ◽  
Block Codes ◽  
Viterbi Decoder ◽  
Space Communications ◽  
Convolutional Coding ◽  
Coding Scheme ◽  
Alternative Approach ◽  
Constraint Length ◽  
Convolutional Encoder ◽  
Digital Communication Systems

In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.

scholarly journals Constraint length inflation in fixed high rate convolutional codes and their impact on performance of O-IDMA

2020 ◽  
Vol 20 (2) ◽  
pp. 837
Author(s):  
Ravi Prakash ◽  
Ajay Kumar Maurya ◽  
Rakesh Kumar Maurya ◽  
B. B. Tiwari
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Technology Use ◽  
Communication Systems ◽  
Multiple Access ◽  
Convolutional Codes ◽  
Combined Effect ◽  
High Rate ◽  
Access Technology ◽  
Constraint Length

<p>To cope up with the higher data rate existing in modern communication systems multiple access technologies has been investigated OIDMA (Optical Interleave Division Multiple Access Technology) is one of the prominent technology use to fulfill this demand. Convolutional codes used in OIDMA systems enhance the performances and reduces the bit error rate of the system. In the present paper, the convolutional codes with increasing number of memory elements are used, the constraint length which depends on number of memory elements are increased with a systematic manner and their combined effect on response of OIDMA system has been observed. Tree inter-leavers in taken into account for analysis purpose and BER with increasing number of users is plotted in graphical and tabular manner.</p>

scholarly journals Design of a High Speed and Low Power Sample and Hold Circuit for 16 Bit ADC

2019 ◽  
Vol 9 (2S3) ◽  
pp. 222-225
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Cmos Technology ◽  
Data Conversion ◽  
Basic Building Block ◽  
Range Resolution ◽  
Sample And Hold ◽  
Present World ◽  
High Range

Data plays an important role in the present world where the communications are becoming so crucial. Data acquisition and communication systems are in need ofhigherresolution (i.e., 16 Bits)ADCs. The successive approximation (SAR) ADCis suitable for medium to high range resolution applications, the basic building block of the ADC is Sample and hold circuit which will perform a key role in data conversion from analog data to corresponding digital data.In this paper an operational amplifier with gain 96.5 dB and phase margin of 770 with UGB of 12 MHz is designed to implement high speed and low power sample and hold (S/H) circuit using 0.18 µm SCL CMOS Technology, for higher bit ADC applications with sampling frequency of 10 MHz consuming 182 µW power operating at 3.3 V.

Sign in / Sign up

Export Citation Format

Share Document