Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework
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2009 ◽
Vol 28
(3)
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pp. 305-315
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Keyword(s):
2005 ◽
Vol 133
(1-4)
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pp. 229-248
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2017 ◽
Vol E100.C
(4)
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pp. 407-415
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2002 ◽
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