Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework

Author(s):  
Qiang Liu ◽  
George A. Constantinides ◽  
Konstantinos Masselos ◽  
Peter Y.K. Cheung
2005 ◽  
Vol 133 (1-4) ◽  
pp. 229-248 ◽  
Author(s):  
Hao Cheng ◽  
Shu-Cherng Fang ◽  
John E. Lavery

2017 ◽  
Vol E100.C (4) ◽  
pp. 407-415
Author(s):  
Minyoung YOON ◽  
Byungjoon KIM ◽  
Jintae KIM ◽  
Sangwook NAM

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