Maximum throughput strategy based on multiuser cooperative mobility under different location distributions in MANETs

2021 ◽  
Author(s):  
Jiquan Xie ◽  
Tutomu Murase
Keyword(s):  
Maximum Throughput

Performance Analysis and Improvement on SIP-Based VoIP Server

2013 ◽  
Vol 284-287 ◽  
pp. 2855-2859
Author(s):  
Li Te Shen ◽  
Shaw Hwa Hwang ◽  
Chi Jung Huang ◽  
Cheng Yu Yeh
Keyword(s):  
Performance Improvement ◽  
Proxy Server ◽  
Packet Size ◽  
Improved Method ◽  
Maximum Throughput ◽  
Streaming Server ◽  
The Media ◽  
Call Setup ◽  
Sip Proxy ◽  
Server System

The performance improvement on SIP-based VoIP server is given in this paper. The signaling server “SIP Proxy Server” and media streaming server “Media Relay Server” are applied. Firstly, the performance of VoIP server is analyzed and evaluated in detail. Then the effective method is applied to improve the performance of VoIP server. In the analysis results of SIP Proxy Server, the CPU time for the registration and call-setup sessions need 3.241 ms and 7.985 ms respectively. Moreover, in the Media Relay Server system, when the packet size from 1 to 32 bytes, the maximum throughput of packet is about 82,000 and 16,000 per second for UDP and TCP respectively. The large the packet, the less throughput is tenable. There are three methods applied to improve the performance. The capacity by 31 times is achieved. The capacity with 3,524 calls for each Media Relay Server is achieved. The improved method proposed in this paper is reasonable.

Adaptive Deep Rider LSTM-enabled Objective Functions for RPL routing in IoT applications

2022 ◽  
Vol 16 (1) ◽  
pp. 0-0
Keyword(s):  
Energy Dissipation ◽  
Objective Function ◽  
Minimum Energy ◽  
Link Quality ◽  
Maximum Throughput ◽  
Routing Metrics ◽  
Energy Prediction ◽  
Iot Applications ◽  
Energy Distance ◽  
Application Requirements

This paper presents a proposed Objective Function (OF) design using various routing metrics for improving the performance of IoT applications. The most important idea of the proposed design is the selection of the routing metrics with respect to the application requirements. The various metrics, such as Energy, Distance, Delay, Link quality, Trust (EDDLT) are used for improving the objective function design of the RPL in various IoT applications. Here, the Adaptive Deep rider LSTM is newly employed for the energy prediction where the Adaptive Deep Rider LSTM is devised by the combination of the adaptive theory with the Rider Adam Algorithm (RAA), and the Deep-Long Short Memory (Deep-LSTM). However, the evaluation of the proposed method is carried out energy dissipation, throughput, and delay by achieving a minimum energy dissipation of 0.549, maximum throughput of 1, and a minimum delay of 0.191, respectively.

scholarly journals Development of Software Defined Radio Algorithm using Mimo OFDM for Short Range Communication

2019 ◽  
Vol 8 (10) ◽  
pp. 3994-4003
Keyword(s):  
Channel Estimation ◽  
Amplitude Modulation ◽  
Software Defined Radio ◽  
Short Range ◽  
Carrier Frequency Offset ◽  
Data Rate ◽  
Spectrum Efficiency ◽  
Beam Forming ◽  
Maximum Throughput ◽  
Mimo Ofdm

In the recent past, the software defined radio (SDR) using Multiple-Input-Multiple-Output Orthogonal Frequency Division Multiplex (OFDM) is implemented to improve the data rate and channel estimation with high spectrum and maximum throughput for short range communication. The short range of communication is established to communicate the data between different nodes placed in the appropriate position using localization technique using SDR MIMO OFDM. The 256-M Array Quadrature Amplitude Modulation (256 M-Ary Quartrature Amplitude Modulation) is applied to SDR MIMO OFDM to reduce Modulation Error Rate (MER) for efficient transmission of data through SDR. The high data rate is achieved by applying the beam-forming equalization technique by applying beam-forming between transmitter and receiver of SDR. The Zero-forcing-beam-forming (ZFBF) equalizer is used in frequency domain to correlate transmitter and receiver to improve the spectrum efficiency better. The synchronization error is reduced in the transceiver of SDR by reducing Carrier Frequency Offset (CFO) mismatch and Sampling Time Offset (STO). The simulation results have proved that the proposed algorithm have better performance in data rate improvement with elimination of CFO mismatch problem to improve the spectrum efficiency and higher range of channel estimation.

scholarly journals Improvement of Spectral Efficiency in Home Area Network using Cognitive Radio Algorithm

2019 ◽  
Vol 8 (12) ◽  
pp. 1129-1131
Keyword(s):  
Cognitive Radio ◽  
Spectrum Sharing ◽  
Queuing Theory ◽  
Primary User ◽  
Cognitive Networks ◽  
Area Network ◽  
Maximum Throughput ◽  
Multiple Channel ◽  
Faster Development ◽  
Home Region

The faster development of wireless communications has made the spectrum ending up with increasingly with more shortage. The idea of CR was proposed to meet the problem of spectrum effectiveness. In the cognitive networks, the SUs are permitted to detect, distinguish and access the frequency bands that are not at present used by the PU’s. the SU’s must outfit with the spectrum access information to use the primary user’s licence in the home region network. We propose a maximum throughput and power based cognitive radio for home region systems (HAN). At the point when there are different SU’s and numerous channels, spectrum sharing must be taken into account. In this paper we additionally propose a system of multiple channel sensing. We consider the interference to PU brought about by the dynamic access and the erroneous spectrum sensing technique. We investigate the obstruction brought about by the secondary user’s through a reestablishment hypothesis. Under the limitation of interference to primary user, the queuing theory is used to overcome this issue and to obtain the higher data rate of SU’s. finally, it is demonstrated that the cyclostationary detection method can be improved when extra channels are accessible.

scholarly journals A streaming multi-class support vector machine classification architecture for embedded systems

2019 ◽  
Vol 16 (3) ◽  
pp. 1286
Author(s):  
Jeevan Sirkunan ◽  
Jia Wei Tang ◽  
Nasir Shaikh-Husin ◽  
Muhammad Nadzir Marsono
Keyword(s):  
Embedded System ◽  
Test Data ◽  
Data Transfer ◽  
Pedestrian Detection ◽  
External Memory ◽  
Support Vector ◽  
Data Input ◽  
Maximum Throughput ◽  
Process Data ◽  
Svm Classification

<p>Pedestrian detection, face detection, speech recognition and object detection are some of the applications that have benefited from hardware-accelerated SVM. SVM classification computational complexity makes it challenging for designing hardware architecture with real-time performance and low power consumption. On an embedded streaming architecture, test data are stored on external memory and transferred in streams to the FPGA device. The hardware<br />implementation for SVM classification needs to be fast enough to keep up with the data transfer speed. Prior implementation throttles data input to avoid overwhelming the computational unit. This results in a bottleneck in overall streaming architecture as maximum throughput could not be obtained. In this work, we propose a streaming architecture multi-class SVM classification for embedded system that is fully pipelined and able to process data continuously with out any need to throttle data stream input. The proposed design is targeted for embedded platform where test data is transferred in streams from an external memory. The architecture was implemented on Altera Cyclone IV platform. Performance analysis on our proposed architecture is done with regards to the number of features and support vectors. For validation, the results obtained is compared with LibSVM. The proposed architecture is able to produce output rate identical to test data input rate.</p>

scholarly journals Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽  
2019 ◽  
Author(s):  
Luka Daoud ◽  
Fady Hussein ◽  
Nader Rafla
Keyword(s):  
High Level Synthesis ◽  
Advanced Encryption Standard ◽  
Data Confidentiality ◽  
Maximum Throughput ◽  
Loop Unrolling ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
High Level ◽  
Dedicated Hardware ◽  
Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

Sign in / Sign up

Export Citation Format

Share Document