This paper primarily focuses on designing a new
Built in self test (BIST) methodology to test the configurable logic
blocks (CLBs) which is the heart of field programmable gate array
(FPGA). The proposed methodology targets stuck-at-0/1 faults on
a RAM cell in an LUT which constitutes about 90% of the total
faults in the CLBs. No extra area overhead is needed to
accommodate the test pattern generators (TPGs) and output
responses analyzers (ORAs) as they are realized by the already
existing configurable resources on the FPGA.A group of CLBs
chosen as block under test (BUT) are configured as
complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to
successfully test the aforementioned faults. The proposed BIST
structure when implemented on Xilinx Virtex-4 FPGA proved
100% fault coverage and minimized test configurations.