This paper presents a performance-oriented placement and routing tool for field-programmable
gate arrays. Using recursive geometric partitioning for simultaneous
placement and global routing, and a graph-based strategy for detailed routing, our tool
optimizes source-sink pathlengths, channel width and total wirelength. Our results
compare favorably with other FPGA layout tools, as measured by the maximum
channel width required to place and route several benchmarks.
This paper presents a router for routing multi-terminal nets in field-programmable gate arrays (FPGAs). The router does not require pre-assignment of routing channels, a phase that is normally accomplished during global routing. This direct routing approach greatly enhances the probability of routing (routability). The multi-terminal routing greatly reduces the total wire length as it approximates a Steiner tree. The total number of segments required to route the circuits is usually less as compared to other routing approaches. The router has generated excellent routing results for some industrial circuits. The memory requirements for this router are very low. The time needed for the routing is linear with respect to the size of the circuit.
Placement and Routing for Performance-Oriented FPGA Layout