Correction prediction: Reducing error correction latency for on-chip memories

2015 ◽  
Author(s):  
Henry Duwe ◽  
Xun Jian ◽  
Rakesh Kumar
Keyword(s):  
Error Correction ◽  
On Chip

scholarly journals A static RAM chip with on-chip error correction

1990 ◽  
Vol 25 (5) ◽  
pp. 1290-1294 ◽  
Author(s):  
T.-D. Chiueh ◽  
R.M. Goodman ◽  
M. Sayano
Keyword(s):  
Error Correction ◽  
Static Ram ◽  
On Chip

Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Error Control ◽  
Low Complexity ◽  
Hardware Complexity ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses

2015 ◽  
Vol 77 (2-3) ◽  
pp. 479-491 ◽  
Author(s):  
Yeow Meng Chee ◽  
Charles J. Colbourn ◽  
Alan Chi Hung Ling ◽  
Hui Zhang ◽  
Xiande Zhang
Keyword(s):  
Low Power ◽  
Error Correction ◽  
Chip Data ◽  
Data Buses ◽  
On Chip ◽  
Crosstalk Avoidance

Single-Event Upset (SEU) in a Dram with On-Chip Error Correction

1987 ◽  
Vol 34 (6) ◽  
pp. 1310-1315 ◽  
Author(s):  
J. A. Zoutendyk ◽  
H. R. Schwartz ◽  
R. K. Watson ◽  
Z. Hasnain ◽  
L. R. Nevill
Keyword(s):  
Error Correction ◽  
Single Event Upset ◽  
Single Event ◽  
On Chip
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