Design, Application, and Verification of the Novel SEU Tolerant Abacus-Type Layouts

Radiation tolerance improvements for advanced technologies have attracted considerable interests in space application. In this paper, the single event upset (SEU) hardened double interlocked storage cell (DICE) D-type flip-flops (DFFs) with abacus-type time-delay cell are proposed and successfully implemented in our test chips. The layout structures of two kinds of abacus-type time-delay cells are illustrated, and their hardening effectiveness are verified by our simulations and heavy ion irradiations. The systematic heavy ion experimental results show that the applied abacus-type time-delay cells can reduce the SEU cross sections of DICE DFFs significantly, and even the SEU immune is observed for the full “0” data pattern. Besides, an apparent test mode dependency of the abacus-type hardened circuits is also observed. The results indicate that the nanoscale abacus structure may be suitable for space application in harsh radiation environment.

The relationship between the single event upset and the order of sensitive transistors in flip-flop layout

Traditionally, it is believed that only reverse biased PN junctions can collect ionized electron-hole pairs. Therefore, only the drain of the transistor in the off-state can be considered as a sensitive node, which is easy to absorb charge and cause upset. This paper finds that on-state transistors can also become sensitive nodes. This paper studies the relationship between SEU and the order of transistors in the flip-flop layout. It is found that the adjacent placement of on-state sensitive transistors can promote the occurrence of SEU, and a targeted hardened plan is proposed. The results of this paper are helpful for the design of the radiation-resistant layout of the flip-flop.

A Strategy to Mitigate Single Event Upset in 14 nm CMOS Bulk FinFET Technology

3D TCAD simulations demonstrated that reducing the distance between the well boundary and NMOS or PMOS can mitigate the cross section of Single Event Upset (SEU) in 14 nm CMOS bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restore currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Different from Dual-interlock cells (DICE) design, under the presence of enough taps to ensure the rapid recovery of well potential, this approach is more effective under heavy ion irradiation of higher LET. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.

Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.