Protection of On-chip Memory Systems against Multiple Cell Upsets Using Double-adjacent Error Correction Codes

AbstractReliability of the memory subsystem is a growing concern in computer architecture and system design. From on-chip embedded memories in Internet-of-Things (IoT) devices and on-chip caches to off-chip main memories, the memory subsystems have become the limiting factor in the overall reliability of computing systems. This is because they are primarily designed to maximize bit storage density; this makes memories particularly sensitive to manufacturing process variation, environmental operating conditions, and aging-induced wearout. This chapter of the book focuses on software managed techniques and novel error correction codes to opportunistically cope with memory errors whenever they occur for improved reliability at minimal cost.

Download Full-text

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

Journal of Circuits System and Computers ◽

10.1142/s0218126622500049 ◽

2021 ◽

pp. 2250004

Author(s):

Jagannath Samanta ◽

Akash Kewat

Keyword(s):

Error Correction ◽

Error Detection ◽

High Speed ◽

Memory Systems ◽

Cache Memory ◽

Error Correction Codes ◽

Parity Check Matrix ◽

Single Error ◽

Check Matrix ◽

Field Programmable

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

Download Full-text

Bidirectional Limited-Magnitude Error Correction Codes for Flash Memories

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e96.a.1602 ◽

2013 ◽

Vol E96.A (7) ◽

pp. 1602-1608 ◽

Cited By ~ 1

Author(s):

Myeongwoon JEON ◽

Jungwoo LEE

Keyword(s):

Error Correction ◽

Error Correction Codes ◽

Flash Memories

Download Full-text

Deep PUF: A Highly Reliable DRAM PUF-Based Authentication for IoT Networks Using Deep Convolutional Neural Networks

Sensors ◽

10.3390/s21062009 ◽

2021 ◽

Vol 21 (6) ◽

pp. 2009

Author(s):

Fatemeh Najafi ◽

Masoud Kaveh ◽

Diego Martín ◽

Mohammad Reza Mosavi

Keyword(s):

Error Correction ◽

Random Access ◽

Error Correction Codes ◽

Access Memory ◽

Deep Convolutional Neural Networks ◽

Device Identification ◽

Physical Unclonable Functions ◽

Server Side ◽

Correction Technique ◽

Reduction Methods

Traditional authentication techniques, such as cryptographic solutions, are vulnerable to various attacks occurring on session keys and data. Physical unclonable functions (PUFs) such as dynamic random access memory (DRAM)-based PUFs are introduced as promising security blocks to enable cryptography and authentication services. However, PUFs are often sensitive to internal and external noises, which cause reliability issues. The requirement of additional robustness and reliability leads to the involvement of error-reduction methods such as error correction codes (ECCs) and pre-selection schemes that cause considerable extra overheads. In this paper, we propose deep PUF: a deep convolutional neural network (CNN)-based scheme using the latency-based DRAM PUFs without the need for any additional error correction technique. The proposed framework provides a higher number of challenge-response pairs (CRPs) by eliminating the pre-selection and filtering mechanisms. The entire complexity of device identification is moved to the server side that enables the authentication of resource-constrained nodes. The experimental results from a 1Gb DDR3 show that the responses under varying conditions can be classified with at least a 94.9% accuracy rate by using CNN. After applying the proposed authentication steps to the classification results, we show that the probability of identification error can be drastically reduced, which leads to a highly reliable authentication.

Download Full-text