SRFTL: An Adaptive Superblock-Based Real-Time Flash Translation Layer for NAND Flash Memory

Author(s):  
Xin Li ◽  
Zhaoyan Shen ◽  
Lei Ju ◽  
Zhiping Jia
2016 ◽  
Vol 2 (1) ◽  
pp. 17-29 ◽  
Author(s):  
Yi Wang ◽  
Zhiwei Qin ◽  
Renhai Chen ◽  
Zili Shao ◽  
Qixin Wang ◽  
...  

2013 ◽  
Vol 464 ◽  
pp. 365-368 ◽  
Author(s):  
Ji Jun Hung ◽  
Kai Bu ◽  
Zhao Lin Sun ◽  
Jie Tao Diao ◽  
Jian Bin Liu

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.


2011 ◽  
Vol 60 (8) ◽  
pp. 1126-1141 ◽  
Author(s):  
Jong-Chan Kim ◽  
Duhee Lee ◽  
Chang-Gun Lee ◽  
Kanghee Kim

Author(s):  
Jong-Chan Kim ◽  
Duhee Lee ◽  
Chang-Gun Lee ◽  
Kanghee Kim ◽  
Eun Yong Ha

2022 ◽  
Vol 21 (1) ◽  
pp. 1-24
Author(s):  
Katherine Missimer ◽  
Manos Athanassoulis ◽  
Richard West

Modern solid-state disks achieve high data transfer rates due to their massive internal parallelism. However, out-of-place updates for flash memory incur garbage collection costs when valid data needs to be copied during space reclamation. The root cause of this extra cost is that solid-state disks are not always able to accurately determine data lifetime and group together data that expires before the space needs to be reclaimed. Real-time systems found in autonomous vehicles, industrial control systems, and assembly-line robots store data from hundreds of sensors and often have predictable data lifetimes. These systems require guaranteed high storage bandwidth for read and write operations by mission-critical real-time tasks. In this article, we depart from the traditional block device interface to guarantee the high throughput needed to process large volumes of data. Using data lifetime information from the application layer, our proposed real-time design, called Telomere , is able to intelligently lay out data in NAND flash memory and eliminate valid page copies during garbage collection. Telomere’s real-time admission control is able to guarantee tasks their required read and write operations within their periods. Under randomly generated tasksets containing 500 tasks, Telomere achieves 30% higher throughput with a 5% storage cost compared to pre-existing techniques.


2013 ◽  
pp. 439-455 ◽  
Author(s):  
Pierre Olivier ◽  
Jalil Boukhobza ◽  
Eric Senn

NAND Flash memories gained a solid foothold in the embedded systems domain due to its attractive characteristics in terms of size, weight, shock resistance, power consumption, and data throughput. Moreover, flash memories tend to be less confined to the embedded domain, as it can be observed through the market explosion of flash-based storage systems (average growth of the NVRAM is reported to be about 69% up to 2015). In this chapter, the authors focus on NAND flash memory NVRAM. After a global presentation of its architecture and very specific constraints, they describe the different ways to manage flash memories in embedded systems which are 1) the use of a hardware Flash Translation Layer (FTL), or 2) a dedicated Flash File System (FFS) software support implemented within the embedded operating system kernel.


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