Flash-Based Storage in Embedded Systems

2013 ◽  
pp. 439-455 ◽  
Author(s):  
Pierre Olivier ◽  
Jalil Boukhobza ◽  
Eric Senn
Keyword(s):  
Embedded Systems ◽  
Flash Memory ◽  
Nand Flash ◽  
Embedded Operating System ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Software Support ◽  
Average Growth ◽  
Shock Resistance ◽  
Flash Translation Layer

NAND Flash memories gained a solid foothold in the embedded systems domain due to its attractive characteristics in terms of size, weight, shock resistance, power consumption, and data throughput. Moreover, flash memories tend to be less confined to the embedded domain, as it can be observed through the market explosion of flash-based storage systems (average growth of the NVRAM is reported to be about 69% up to 2015). In this chapter, the authors focus on NAND flash memory NVRAM. After a global presentation of its architecture and very specific constraints, they describe the different ways to manage flash memories in embedded systems which are 1) the use of a hardware Flash Translation Layer (FTL), or 2) a dedicated Flash File System (FFS) software support implemented within the embedded operating system kernel.

PCI Express-Based NVMe Solid State Disk

2013 ◽  
Vol 464 ◽  
pp. 365-368 ◽  
Author(s):  
Ji Jun Hung ◽  
Kai Bu ◽  
Zhao Lin Sun ◽  
Jie Tao Diao ◽  
Jian Bin Liu
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Detailed Design ◽  
Pci Express ◽  
Storage Media ◽  
Solid State Disk ◽  
Memory Card ◽  
Non Volatile Memory ◽  
Flash Translation Layer

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

scholarly journals Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1152
Author(s):  
Fei Chen ◽  
Bo Chen ◽  
Hongzhe Lin ◽  
Yachen Kong ◽  
Xin Liu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Temperature Effects ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Charge Trap ◽  
Fundamental Factor ◽  
Temperature Impacts ◽  
Raw Bit Error Rate

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

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