Design of fully adaptive routing for partially interconnected cross-link mesh topology for Network on Chip

2017 ◽  
Author(s):  
Rohit Mahar ◽  
Sudhanshu Choudhary ◽  
Jyoti Khichar
Keyword(s):  
Adaptive Routing ◽  
Network On Chip ◽  
Cross Link ◽  
Mesh Topology ◽  
Fully Adaptive ◽  
On Chip

Comparative Performance Analysis of 
Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based 
Network-On-Chip

2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Injection Rate ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Comparative Performance ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
Similar Vein ◽  
On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

scholarly journals Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

2019 ◽  
Vol 14 (2) ◽  
pp. 802
Author(s):  
Ng Yen Phing ◽  
M.N.Mohd Warip ◽  
Phaklen Ehkan ◽  
R Badlishah Ahmad ◽  
F.W. Zulkefli
Keyword(s):  
Power Consumption ◽  
Small Area ◽  
Network On Chip ◽  
Low Power Consumption ◽  
Cross Link ◽  
Ring Topology ◽  
Mesh Topology ◽  
Average Area ◽  
On Chip ◽  
Point To Point

<span>The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.</span>

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs

2019 ◽  
Vol 28 (12) ◽  
pp. 1950202 ◽  
Author(s):  
Khyamling Parane ◽  
B. M. Prabhu Prasad ◽  
Basavaraj Talawar
Keyword(s):  
Design Space Exploration ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Tree Topology ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
On Chip ◽  
Congestion Aware

Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the [Formula: see text] mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the [Formula: see text] mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.

An energy- and buffer-aware fully adaptive routing algorithm for Network-on-Chip

2013 ◽  
Vol 44 (2) ◽  
pp. 137-144 ◽  
Author(s):  
Junhui Wang ◽  
Huaxi Gu ◽  
Yintang Yang ◽  
Kun Wang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Fully Adaptive ◽  
On Chip

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

Sign in / Sign up

Export Citation Format

Share Document