Design of UWB CMOS CG-LNA with Improved Noise Figure using Noise Cancellation Technique

2019 ◽  
Author(s):  
Naveen Singh ◽  
Narendra Yadava ◽  
R. K. Chauhan
Keyword(s):  
Noise Figure ◽  
Noise Cancellation

A Power-Efficient Noise Canceling Technique Using Signal-Suppression Feed-Forward for Wideband LNAs

2015 ◽  
Vol 643 ◽  
pp. 109-116
Author(s):  
Daiki Oki ◽  
Satoru Kawauchi ◽  
Cong Bing Li ◽  
Masataka Kamiyama ◽  
Seiichi Banba ◽  
...  
Keyword(s):  
Power Consumption ◽  
Input Signal ◽  
Noise Figure ◽  
Wide Band ◽  
Noise Cancellation ◽  
Cmos Process ◽  
Feed Forward ◽  
Power Efficient ◽  
Signal Suppression ◽  
Noise Canceling

This paper presents a power-efficient noise-canceling technique based on the feed-forward amplifiers, considering a fundamental tradeoff between noise figure (NF) and power consumption in the design of wide-band amplifiers. By suppressing the input signal of the noise cancellation amplifier, the nonlinear effect on the amplifier can be reduced, as well as the power consumption can be smaller. Furthermore, as a lower gain of the noise-canceling sub-amplifier can be achieved simultaneously, further reduction of the power consumption becomes possible. The verification of the proposed technique is conducted with Spectre simulation using 90nm CMOS process.

Design Analysis of Inductorless Active Loaded Low Power UWB LNA Using Noise Cancellation Technique

Frequenz ◽  
2020 ◽  
Vol 74 (3-4) ◽  
pp. 137-144 ◽  
Author(s):  
Dheeraj Kalra ◽  
Manish Kumar ◽  
Aasheesh Shukla ◽  
Laxman Singh ◽  
Zainul Abdin Jaffery
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Broad Band ◽  
Wide Band ◽  
Cmos Technology ◽  
Noise Cancellation ◽  
Low Noise ◽  
Design Analysis ◽  
Common Source ◽  
Power Gain

AbstractThis paper includes a design analysis of an inductorless low-power (LP) low-noise amplifier (LNA) with active load for Ultra Wide Band (UWB) applications. The proposed LNA consists of two parallel paths, one is the common source (CS) path and second is the CG path. The CG path has the edge advantage of improving overall Noise figure (NF) due to wide band impedance matching in UWB, while the CS path provides high power gain. A method for noise cancellation is adopted, to reduce the noise of CS path with the help of CG path. The proposed LNA successfully simulated in 90 nm CMOS technology. The results of proposed work indicate optimization at frequency 5.70 GHz with 3 dB bandwidth of 4.3 GHz–8.9 GHz. All simulations have been done for a range of frequency 03 GHz–13 GHz in Cadence virtuoso software. The results quoted 1.15 dB NF, −18.12 dB S11, 13.7 dB S21, maximum operating power gain (GP) 11.756 dB at frequency 5.7 GHz and available power gain (GA) is 10.17 dB at frequency 8.61 GHz, with 0.6 V, 0.92 mW broad band LNA.

THE GENERALIZED PREDICTIV COMMAND APPLIED TO THE NOISE CANCELLATION

1990 ◽  
Vol 51 (C2) ◽  
pp. C2-765-C2-768
Author(s):  
C. DUVERMY ◽  
E. ORTOLA
Keyword(s):  
Noise Cancellation

On Wafer Noise Figure De-Embedding Method for CMOS Differential LNA

2020 ◽  
Vol E103.C (7) ◽  
pp. 335-340
Author(s):  
Maizan MUHAMAD ◽  
Norhayati SOIN ◽  
Harikrishnan RAMIAH
Keyword(s):  
Noise Figure ◽  
Embedding Method

Design low noise figure phemt lna using inductive drain feedback for WIMAX application

2014 ◽  
Author(s):  
K. Pongot ◽  
J.S. Hamidon ◽  
A. Ahmad ◽  
M.K. Suaidi ◽  
A.H. Hamidon ◽  
...  
Keyword(s):  
Noise Figure ◽  
Low Noise

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

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